From patchwork Wed Oct 21 03:31:31 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Satheesh Paul Antonysamy X-Patchwork-Id: 81658 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 23B21A04DD; Wed, 21 Oct 2020 05:31:46 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 8FC9FAC7C; Wed, 21 Oct 2020 05:31:43 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by dpdk.org (Postfix) with ESMTP id 3AB51AC71 for ; Wed, 21 Oct 2020 05:31:42 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 09L3QEhX012493 for ; Tue, 20 Oct 2020 20:31:40 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=bungkRP95BhjE3eLT7aEZYy5PPzifC1amWSvvInSzKg=; b=intyRFbE+N04IpQLpnS7MTcP0C5fP32VJ+2ofhPrSG5GNIaAhbYRl50YBsNISGyMQN6i UBi0QWaWE1N8ohUQF5h9wEiN0va5BtQK+5duk5Qewr6Fz34KtLM/Rg9wgBU5FTwJGiqB ilb4GKnoS9qlUJXGXQN/8h9gIpqVH9JcowdqJneJXE3JuXOKohAfYvfO8FWb1IjbVERl zrf+1/vWBFGRVU5GHPTEZy6JUdAkLZ3t0fssPmQIq9eI0YkeW2yIy1aSWIseOzmOx68K OUthhlGMzNjXVOPlCijn2ntIzJkqeMWOz/ABZzHIAGT8zX13Xh/Lv2p/SJ07xMzMBF7G +Q== Received: from sc-exch03.marvell.com ([199.233.58.183]) by mx0b-0016f401.pphosted.com with ESMTP id 34804nuc30-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Tue, 20 Oct 2020 20:31:40 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by SC-EXCH03.marvell.com (10.93.176.83) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 20 Oct 2020 20:31:38 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 20 Oct 2020 20:31:38 -0700 Received: from localhost.localdomain (unknown [10.28.34.33]) by maili.marvell.com (Postfix) with ESMTP id 323C83F703F; Tue, 20 Oct 2020 20:31:36 -0700 (PDT) From: To: Jerin Jacob , Nithin Dabilpuram , Kiran Kumar K CC: , Satheesh Paul Date: Wed, 21 Oct 2020 09:01:31 +0530 Message-ID: <20201021033131.1743984-1-psatheesh@marvell.com> X-Mailer: git-send-email 2.25.4 MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235, 18.0.737 definitions=2020-10-21_02:2020-10-20, 2020-10-21 signatures=0 Subject: [dpdk-dev] [PATCH] net/octeontx2: support for VF base steering rule X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Satheesh Paul Adds support for merging a base steering rule with all flow rules created on a VF. Signed-off-by: Satheesh Paul Acked-by: Jerin Jacob --- drivers/net/octeontx2/otx2_flow.c | 2 ++ drivers/net/octeontx2/otx2_flow.h | 1 + drivers/net/octeontx2/otx2_flow_utils.c | 19 ++++++++++++++++++- 3 files changed, 21 insertions(+), 1 deletion(-) diff --git a/drivers/net/octeontx2/otx2_flow.c b/drivers/net/octeontx2/otx2_flow.c index e07cea709..a5900f349 100644 --- a/drivers/net/octeontx2/otx2_flow.c +++ b/drivers/net/octeontx2/otx2_flow.c @@ -605,6 +605,8 @@ otx2_flow_create(struct rte_eth_dev *dev, goto err_exit; } + parse_state.is_vf = otx2_dev_is_vf(hw); + rc = flow_program_npc(&parse_state, mbox, &hw->npc_flow); if (rc != 0) { rte_flow_error_set(error, EIO, diff --git a/drivers/net/octeontx2/otx2_flow.h b/drivers/net/octeontx2/otx2_flow.h index 1f118c408..30a823c8a 100644 --- a/drivers/net/octeontx2/otx2_flow.h +++ b/drivers/net/octeontx2/otx2_flow.h @@ -213,6 +213,7 @@ struct otx2_parse_state { uint8_t flags[NPC_MAX_LID]; uint8_t *mcam_data; /* point to flow->mcam_data + key_len */ uint8_t *mcam_mask; /* point to flow->mcam_mask + key_len */ + bool is_vf; }; struct otx2_flow_item_info { diff --git a/drivers/net/octeontx2/otx2_flow_utils.c b/drivers/net/octeontx2/otx2_flow_utils.c index 6215a542f..9a0a5f9fb 100644 --- a/drivers/net/octeontx2/otx2_flow_utils.c +++ b/drivers/net/octeontx2/otx2_flow_utils.c @@ -884,11 +884,13 @@ flow_check_preallocated_entry_cache(struct otx2_mbox *mbox, int otx2_flow_mcam_alloc_and_write(struct rte_flow *flow, struct otx2_mbox *mbox, - __rte_unused struct otx2_parse_state *pst, + struct otx2_parse_state *pst, struct otx2_npc_flow_info *flow_info) { int use_ctr = (flow->ctr_id == NPC_COUNTER_NONE ? 0 : 1); + struct npc_mcam_read_base_rule_rsp *base_rule_rsp; struct npc_mcam_write_entry_req *req; + struct mcam_entry *base_entry; struct mbox_msghdr *rsp; uint16_t ctr = ~(0); int rc, idx; @@ -906,6 +908,21 @@ otx2_flow_mcam_alloc_and_write(struct rte_flow *flow, struct otx2_mbox *mbox, otx2_flow_mcam_free_counter(mbox, ctr); return NPC_MCAM_ALLOC_FAILED; } + + if (pst->is_vf) { + (void)otx2_mbox_alloc_msg_npc_read_base_steer_rule(mbox); + rc = otx2_mbox_process_msg(mbox, (void *)&base_rule_rsp); + if (rc) { + otx2_err("Failed to fetch VF's base MCAM entry"); + return rc; + } + base_entry = &base_rule_rsp->entry_data; + for (idx = 0; idx < OTX2_MAX_MCAM_WIDTH_DWORDS; idx++) { + flow->mcam_data[idx] |= base_entry->kw[idx]; + flow->mcam_mask[idx] |= base_entry->kw_mask[idx]; + } + } + req = otx2_mbox_alloc_msg_npc_mcam_write_entry(mbox); req->set_cntr = use_ctr; req->cntr = ctr;