From patchwork Tue Oct 20 22:48:27 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 81633 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id EEE13A04DD; Wed, 21 Oct 2020 00:45:36 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id C2290ACA7; Wed, 21 Oct 2020 00:45:00 +0200 (CEST) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by dpdk.org (Postfix) with ESMTP id 6E201AC99 for ; Wed, 21 Oct 2020 00:44:56 +0200 (CEST) IronPort-SDR: 0eq0ZqHk5IuY1Mr4e4t7qdAnRUQVd/X9SbFKgAe2q0I3lHwfJNJf8YsXMTUAXDJmA/nL5keGem z8K0YWJwag4g== X-IronPort-AV: E=McAfee;i="6000,8403,9780"; a="166510575" X-IronPort-AV: E=Sophos;i="5.77,399,1596524400"; d="scan'208";a="166510575" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Oct 2020 15:44:54 -0700 IronPort-SDR: zxSHq0w1GHNXZmptfWpL485ohEyUtTolz/HhUNeoQfyEx18EfsU3G26cznmat5+r+CLFYQElRp fRzfyZ82UlnQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,399,1596524400"; d="scan'208";a="533254521" Received: from dpdk51.sh.intel.com ([10.67.111.142]) by orsmga005.jf.intel.com with ESMTP; 20 Oct 2020 15:44:53 -0700 From: Qi Zhang To: qiming.yang@intel.com Cc: dev@dpdk.org, Qi Zhang , Amir Shay Date: Wed, 21 Oct 2020 06:48:27 +0800 Message-Id: <20201020224846.1592682-3-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.25.4 In-Reply-To: <20201020224846.1592682-1-qi.z.zhang@intel.com> References: <20201020224846.1592682-1-qi.z.zhang@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH 02/21] net/ice/base: add NVM Write Response flags X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Added NVM Write Admin Command (0x703) ARQ response flags - as returned in "Response flags" field. Three flags are supported: POR, PERST and EMPR. All indicate the type of reset required to get the NVM bank update effective. Signed-off-by: Amir Shay Signed-off-by: Qi Zhang --- drivers/net/ice/base/ice_adminq_cmd.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/net/ice/base/ice_adminq_cmd.h b/drivers/net/ice/base/ice_adminq_cmd.h index bc71ec5317..9db50de11c 100644 --- a/drivers/net/ice/base/ice_adminq_cmd.h +++ b/drivers/net/ice/base/ice_adminq_cmd.h @@ -1654,6 +1654,9 @@ struct ice_aqc_nvm { #define ICE_AQC_NVM_REVERT_LAST_ACTIV BIT(6) /* Write Activate only */ #define ICE_AQC_NVM_ACTIV_SEL_MASK MAKEMASK(0x7, 3) #define ICE_AQC_NVM_FLASH_ONLY BIT(7) +#define ICE_AQC_NVM_POR_FLAG 0 /* Used by NVM Write completion on ARQ */ +#define ICE_AQC_NVM_PERST_FLAG 1 +#define ICE_AQC_NVM_EMPR_FLAG 2 __le16 module_typeid; __le16 length; #define ICE_AQC_NVM_ERASE_LEN 0xFFFF