[v9,09/18] net/ice: add checks for max SIMD bitwidth
diff mbox series

Message ID 20201016142742.87297-10-ciara.power@intel.com
State Superseded
Delegated to: David Marchand
Headers show
Series
  • add max SIMD bitwidth to EAL
Related show

Checks

Context Check Description
ci/checkpatch success coding style OK

Commit Message

Ciara Power Oct. 16, 2020, 2:27 p.m. UTC
When choosing a vector path to take, an extra condition must be
satisfied to ensure the max SIMD bitwidth allows for the CPU enabled
path.

Cc: Qiming Yang <qiming.yang@intel.com>
Cc: Qi Zhang <qi.z.zhang@intel.com>

Signed-off-by: Ciara Power <ciara.power@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>

---
v4: Updated enum name.
---
 drivers/net/ice/ice_rxtx.c | 20 ++++++++++++++------
 1 file changed, 14 insertions(+), 6 deletions(-)

Patch
diff mbox series

diff --git a/drivers/net/ice/ice_rxtx.c b/drivers/net/ice/ice_rxtx.c
index 79e6df11f4..a1a6d4ac56 100644
--- a/drivers/net/ice/ice_rxtx.c
+++ b/drivers/net/ice/ice_rxtx.c
@@ -2989,7 +2989,9 @@  ice_set_rx_function(struct rte_eth_dev *dev)
 	bool use_avx2 = false;
 
 	if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
-		if (!ice_rx_vec_dev_check(dev) && ad->rx_bulk_alloc_allowed) {
+		if (!ice_rx_vec_dev_check(dev) && ad->rx_bulk_alloc_allowed &&
+				rte_get_max_simd_bitwidth()
+				>= RTE_SIMD_128) {
 			ad->rx_vec_allowed = true;
 			for (i = 0; i < dev->data->nb_rx_queues; i++) {
 				rxq = dev->data->rx_queues[i];
@@ -2999,8 +3001,10 @@  ice_set_rx_function(struct rte_eth_dev *dev)
 				}
 			}
 
-			if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||
-			rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1)
+			if ((rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||
+			rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) &&
+					rte_get_max_simd_bitwidth()
+					>= RTE_SIMD_256)
 				use_avx2 = true;
 
 		} else {
@@ -3167,7 +3171,9 @@  ice_set_tx_function(struct rte_eth_dev *dev)
 	bool use_avx2 = false;
 
 	if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
-		if (!ice_tx_vec_dev_check(dev)) {
+		if (!ice_tx_vec_dev_check(dev) &&
+				rte_get_max_simd_bitwidth()
+				>= RTE_SIMD_128) {
 			ad->tx_vec_allowed = true;
 			for (i = 0; i < dev->data->nb_tx_queues; i++) {
 				txq = dev->data->tx_queues[i];
@@ -3177,8 +3183,10 @@  ice_set_tx_function(struct rte_eth_dev *dev)
 				}
 			}
 
-			if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||
-			rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1)
+			if ((rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||
+			rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) &&
+					rte_get_max_simd_bitwidth()
+					>= RTE_SIMD_256)
 				use_avx2 = true;
 
 		} else {