From patchwork Thu Sep 24 12:12:26 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Rybchenko X-Patchwork-Id: 78731 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id EAE5EA04B1; Thu, 24 Sep 2020 14:22:47 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 1F5841E4C8; Thu, 24 Sep 2020 14:14:18 +0200 (CEST) Received: from dispatch1-us1.ppe-hosted.com (dispatch1-us1.ppe-hosted.com [148.163.129.52]) by dpdk.org (Postfix) with ESMTP id CB9B91DE35 for ; Thu, 24 Sep 2020 14:13:06 +0200 (CEST) Received: from mx1-us1.ppe-hosted.com (unknown [10.7.65.60]) by dispatch1-us1.ppe-hosted.com (PPE Hosted ESMTP Server) with ESMTP id 579A76005E for ; Thu, 24 Sep 2020 12:13:06 +0000 (UTC) Received: from us4-mdac16-37.ut7.mdlocal (unknown [10.7.66.156]) by mx1-us1.ppe-hosted.com (PPE Hosted ESMTP Server) with ESMTP id 55F08200A0 for ; Thu, 24 Sep 2020 12:13:06 +0000 (UTC) X-Virus-Scanned: Proofpoint Essentials engine Received: from mx1-us1.ppe-hosted.com (unknown [10.7.65.200]) by mx1-us1.ppe-hosted.com (PPE Hosted ESMTP Server) with ESMTPS id A28F11C005C for ; Thu, 24 Sep 2020 12:13:05 +0000 (UTC) Received: from webmail.solarflare.com (uk.solarflare.com [193.34.186.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-SHA384 (256/256 bits)) (No client certificate requested) by mx1-us1.ppe-hosted.com (PPE Hosted ESMTP Server) with ESMTPS id 39CFD80005A for ; Thu, 24 Sep 2020 12:13:05 +0000 (UTC) Received: from ukex01.SolarFlarecom.com (10.17.10.4) by ukex01.SolarFlarecom.com (10.17.10.4) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 24 Sep 2020 13:12:48 +0100 Received: from opal.uk.solarflarecom.com (10.17.10.1) by ukex01.SolarFlarecom.com (10.17.10.4) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 24 Sep 2020 13:12:48 +0100 Received: from ukv-loginhost.uk.solarflarecom.com (ukv-loginhost.uk.solarflarecom.com [10.17.10.39]) by opal.uk.solarflarecom.com (8.13.8/8.13.8) with ESMTP id 08OCCmeU026094; Thu, 24 Sep 2020 13:12:48 +0100 Received: from ukv-loginhost.uk.solarflarecom.com (localhost [127.0.0.1]) by ukv-loginhost.uk.solarflarecom.com (Postfix) with ESMTP id 5CD891613A9; Thu, 24 Sep 2020 13:12:48 +0100 (BST) From: Andrew Rybchenko To: CC: Igor Romanov Date: Thu, 24 Sep 2020 13:12:26 +0100 Message-ID: <1600949555-28043-52-git-send-email-arybchenko@solarflare.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1600949555-28043-1-git-send-email-arybchenko@solarflare.com> References: <1600764594-14752-1-git-send-email-arybchenko@solarflare.com> <1600949555-28043-1-git-send-email-arybchenko@solarflare.com> MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-12.5.0.1300-8.6.1012-25674.003 X-TM-AS-Result: No-6.347300-8.000000-10 X-TMASE-MatchedRID: +0fscSjG5oc1+o7k1G1Nsf3HILfxLV/9eouvej40T4htw+n+iKWyyABJ DO15WqH4lUCS+T43Hcy9gZrT7uIToMpY2Ci+polznFVnNmvv47tLXPA26IG0hN9RlPzeVuQQQEC MXtkIBFZ0U4rGHlQpbPYSjSdarl3/+gtEW3D/QKaHjFnwsKDMDC9Xl/s/QdUMuyL9jjE2skEWXb bsSFp0wcKUy0IWNZvl4BvGwuuszG+LA5FCQxdGvE+zv2ByYSDQfLNHMurfykged11F9IsKFAknl zYrXW3xGZx9oY8DzNHA7V1UWABhghp6rGfLEa9i4jRkIImnX0OC0NRF+4xj4NSNWqsiFFWqNTqH vNfE9UEzswktlxv7q2G474XgMsqlkfRhdidsajMURSScn+QSXt0H8LFZNFG7hqz53n/yPnoB5ZT RzcnhDQCrPP5q7dr9Gv5T3m92cgDWyNcAFRGx8boOfFLgUu3n X-TM-AS-User-Approved-Sender: Yes X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--6.347300-8.000000 X-TMASE-Version: SMEX-12.5.0.1300-8.6.1012-25674.003 X-MDID: 1600949586-fyuCbfdULx93 Subject: [dpdk-dev] [PATCH v3 51/60] common/sfc_efx/base: replace PCI efsys macros with functions X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Igor Romanov efsys macros that manipulate PCI devices cannot be defined in common sfc_efx DPDK driver since in DPDK build the bus drivers that provide required functionality are built after common drivers. Replace the macros with function callbacks to remove that build dependency. Drivers now should pass the callbacks directly to efx function instead of defining implementation in efsys. Signed-off-by: Igor Romanov Signed-off-by: Andrew Rybchenko Reviewed-by: Andy Moreton --- drivers/common/sfc_efx/base/efx.h | 29 ++++++++++++++++++++ drivers/common/sfc_efx/base/efx_impl.h | 4 +++ drivers/common/sfc_efx/base/efx_nic.c | 3 ++- drivers/common/sfc_efx/base/efx_pci.c | 34 +++++++++++++----------- drivers/common/sfc_efx/base/rhead_impl.h | 1 + drivers/common/sfc_efx/base/rhead_pci.c | 8 +++--- 6 files changed, 60 insertions(+), 19 deletions(-) diff --git a/drivers/common/sfc_efx/base/efx.h b/drivers/common/sfc_efx/base/efx.h index 4a0a1231dc..7e747e6122 100644 --- a/drivers/common/sfc_efx/base/efx.h +++ b/drivers/common/sfc_efx/base/efx.h @@ -82,6 +82,34 @@ efx_family( #if EFSYS_OPT_PCI +typedef struct efx_pci_ops_s { + /* + * Function for reading PCIe configuration space. + * + * espcp System-specific PCIe device handle; + * offset Offset inside PCIe configuration space to start reading + * from; + * edp EFX DWORD structure that should be populated by function + * in little-endian order; + * + * Returns status code, 0 on success, any other value on error. + */ + efx_rc_t (*epo_config_readd)(efsys_pci_config_t *espcp, + uint32_t offset, efx_dword_t *edp); + /* + * Function for finding PCIe memory bar handle by its index from a PCIe + * device handle. The found memory bar is available in read-only mode. + * + * configp System-specific PCIe device handle; + * index Memory bar index; + * memp Pointer to the found memory bar handle; + * + * Returns status code, 0 on success, any other value on error. + */ + efx_rc_t (*epo_find_mem_bar)(efsys_pci_config_t *configp, + int index, efsys_bar_t *memp); +} efx_pci_ops_t; + /* Determine EFX family and perform lookup of the function control window * * The function requires PCI config handle from which all memory bars can @@ -95,6 +123,7 @@ efx_family_probe_bar( __in uint16_t venid, __in uint16_t devid, __in efsys_pci_config_t *espcp, + __in const efx_pci_ops_t *epop, __out efx_family_t *efp, __out efx_bar_region_t *ebrp); diff --git a/drivers/common/sfc_efx/base/efx_impl.h b/drivers/common/sfc_efx/base/efx_impl.h index be3f3f6bf5..f58586bee0 100644 --- a/drivers/common/sfc_efx/base/efx_impl.h +++ b/drivers/common/sfc_efx/base/efx_impl.h @@ -1588,6 +1588,7 @@ LIBEFX_INTERNAL extern __checkReturn efx_rc_t efx_pci_config_find_next_ext_cap( __in efsys_pci_config_t *espcp, + __in const efx_pci_ops_t *epop, __in uint16_t cap_id, __inout size_t *offsetp); @@ -1602,6 +1603,7 @@ LIBEFX_INTERNAL extern __checkReturn efx_rc_t efx_pci_config_next_ext_cap( __in efsys_pci_config_t *espcp, + __in const efx_pci_ops_t *epop, __inout size_t *offsetp); /* @@ -1614,6 +1616,7 @@ LIBEFX_INTERNAL extern __checkReturn efx_rc_t efx_pci_find_next_xilinx_cap_table( __in efsys_pci_config_t *espcp, + __in const efx_pci_ops_t *epop, __inout size_t *pci_cap_offsetp, __out unsigned int *xilinx_tbl_barp, __out efsys_dma_addr_t *xilinx_tbl_offsetp); @@ -1629,6 +1632,7 @@ LIBEFX_INTERNAL extern __checkReturn efx_rc_t efx_pci_read_ext_cap_xilinx_table( __in efsys_pci_config_t *espcp, + __in const efx_pci_ops_t *epop, __in size_t cap_offset, __out unsigned int *barp, __out efsys_dma_addr_t *offsetp); diff --git a/drivers/common/sfc_efx/base/efx_nic.c b/drivers/common/sfc_efx/base/efx_nic.c index dcf0987ebf..a78c4c3737 100644 --- a/drivers/common/sfc_efx/base/efx_nic.c +++ b/drivers/common/sfc_efx/base/efx_nic.c @@ -110,6 +110,7 @@ efx_family_probe_bar( __in uint16_t venid, __in uint16_t devid, __in efsys_pci_config_t *espcp, + __in const efx_pci_ops_t *epop, __out efx_family_t *efp, __out efx_bar_region_t *ebrp) { @@ -121,7 +122,7 @@ efx_family_probe_bar( #if EFSYS_OPT_RIVERHEAD case EFX_PCI_DEVID_RIVERHEAD: case EFX_PCI_DEVID_RIVERHEAD_VF: - rc = rhead_pci_nic_membar_lookup(espcp, ebrp); + rc = rhead_pci_nic_membar_lookup(espcp, epop, ebrp); if (rc == 0) *efp = EFX_FAMILY_RIVERHEAD; diff --git a/drivers/common/sfc_efx/base/efx_pci.c b/drivers/common/sfc_efx/base/efx_pci.c index bdf995cf84..1e7307476f 100644 --- a/drivers/common/sfc_efx/base/efx_pci.c +++ b/drivers/common/sfc_efx/base/efx_pci.c @@ -12,6 +12,7 @@ __checkReturn efx_rc_t efx_pci_config_next_ext_cap( __in efsys_pci_config_t *espcp, + __in const efx_pci_ops_t *epop, __inout size_t *offsetp) { efx_dword_t hdr; @@ -26,9 +27,9 @@ efx_pci_config_next_ext_cap( if (*offsetp == 0) { *offsetp = ESE_GZ_PCI_BASE_CONFIG_SPACE_SIZE; } else { - EFSYS_PCI_CONFIG_READD(espcp, *offsetp + + rc = epop->epo_config_readd(espcp, *offsetp + (EFX_LOW_BIT(ESF_GZ_PCI_EXPRESS_XCAP_ID) / 8), - &hdr, &rc); + &hdr); if (rc != 0) { rc = EIO; goto fail2; @@ -58,6 +59,7 @@ efx_pci_config_next_ext_cap( __checkReturn efx_rc_t efx_pci_config_find_next_ext_cap( __in efsys_pci_config_t *espcp, + __in const efx_pci_ops_t *epop, __in uint16_t cap_id, __inout size_t *offsetp) { @@ -73,7 +75,7 @@ efx_pci_config_find_next_ext_cap( position = *offsetp; while (1) { - rc = efx_pci_config_next_ext_cap(espcp, &position); + rc = efx_pci_config_next_ext_cap(espcp, epop, &position); if (rc != 0) { if (rc == ENOENT) break; @@ -81,9 +83,9 @@ efx_pci_config_find_next_ext_cap( goto fail2; } - EFSYS_PCI_CONFIG_READD(espcp, position + + rc = epop->epo_config_readd(espcp, position + (EFX_LOW_BIT(ESF_GZ_PCI_EXPRESS_XCAP_ID) / 8), - &hdr, &rc); + &hdr); if (rc != 0) { rc = EIO; goto fail3; @@ -116,6 +118,7 @@ efx_pci_config_find_next_ext_cap( __checkReturn efx_rc_t efx_pci_find_next_xilinx_cap_table( __in efsys_pci_config_t *espcp, + __in const efx_pci_ops_t *epop, __inout size_t *pci_cap_offsetp, __out unsigned int *xilinx_tbl_barp, __out efsys_dma_addr_t *xilinx_tbl_offsetp) @@ -134,7 +137,7 @@ efx_pci_find_next_xilinx_cap_table( unsigned int tbl_bar; efsys_dma_addr_t tbl_offset; - rc = efx_pci_config_find_next_ext_cap(espcp, + rc = efx_pci_config_find_next_ext_cap(espcp, epop, ESE_GZ_PCI_EXPRESS_XCAP_ID_VNDR, &cap_offset); if (rc != 0) { if (rc == ENOENT) @@ -149,7 +152,7 @@ efx_pci_find_next_xilinx_cap_table( * locator. Try to read it and skip it if the capability is * not the locator. */ - rc = efx_pci_read_ext_cap_xilinx_table(espcp, cap_offset, + rc = efx_pci_read_ext_cap_xilinx_table(espcp, epop, cap_offset, &tbl_bar, &tbl_offset); if (rc == 0) { *xilinx_tbl_barp = tbl_bar; @@ -183,6 +186,7 @@ efx_pci_find_next_xilinx_cap_table( __checkReturn efx_rc_t efx_pci_read_ext_cap_xilinx_table( __in efsys_pci_config_t *espcp, + __in const efx_pci_ops_t *epop, __in size_t cap_offset, __out unsigned int *barp, __out efsys_dma_addr_t *offsetp) @@ -199,9 +203,9 @@ efx_pci_read_ext_cap_xilinx_table( efsys_dma_addr_t offset; efx_rc_t rc; - EFSYS_PCI_CONFIG_READD(espcp, cap_offset + + rc = epop->epo_config_readd(espcp, cap_offset + (EFX_LOW_BIT(ESF_GZ_PCI_EXPRESS_XCAP_ID) / 8), - &cap_hdr, &rc); + &cap_hdr); if (rc != 0) { rc = EIO; goto fail1; @@ -213,9 +217,9 @@ efx_pci_read_ext_cap_xilinx_table( goto fail2; } - EFSYS_PCI_CONFIG_READD(espcp, vsec_offset + + rc = epop->epo_config_readd(espcp, vsec_offset + (EFX_LOW_BIT(ESF_GZ_VSEC_ID) / 8), - &vsec.eo_dword[0], &rc); + &vsec.eo_dword[0]); if (rc != 0) { rc = EIO; goto fail3; @@ -240,9 +244,9 @@ efx_pci_read_ext_cap_xilinx_table( goto fail5; } - EFSYS_PCI_CONFIG_READD(espcp, vsec_offset + + rc = epop->epo_config_readd(espcp, vsec_offset + (EFX_LOW_BIT(ESF_GZ_VSEC_TBL_BAR) / 8), - &vsec.eo_dword[1], &rc); + &vsec.eo_dword[1]); if (rc != 0) { rc = EIO; goto fail6; @@ -252,9 +256,9 @@ efx_pci_read_ext_cap_xilinx_table( offset_low = EFX_OWORD_FIELD32(vsec, ESF_GZ_VSEC_TBL_OFF_LO); if (vsec_len >= ESE_GZ_VSEC_LEN_HIGH_OFFT) { - EFSYS_PCI_CONFIG_READD(espcp, vsec_offset + + rc = epop->epo_config_readd(espcp, vsec_offset + (EFX_LOW_BIT(ESF_GZ_VSEC_TBL_OFF_HI) / 8), - &vsec.eo_dword[2], &rc); + &vsec.eo_dword[2]); if (rc != 0) { rc = EIO; goto fail7; diff --git a/drivers/common/sfc_efx/base/rhead_impl.h b/drivers/common/sfc_efx/base/rhead_impl.h index 4d5307d18b..3383c47ec6 100644 --- a/drivers/common/sfc_efx/base/rhead_impl.h +++ b/drivers/common/sfc_efx/base/rhead_impl.h @@ -461,6 +461,7 @@ LIBEFX_INTERNAL extern __checkReturn efx_rc_t rhead_pci_nic_membar_lookup( __in efsys_pci_config_t *espcp, + __in const efx_pci_ops_t *epop, __out efx_bar_region_t *ebrp); #endif /* EFSYS_OPT_PCI */ diff --git a/drivers/common/sfc_efx/base/rhead_pci.c b/drivers/common/sfc_efx/base/rhead_pci.c index dfb163b96d..0f4b4cb910 100644 --- a/drivers/common/sfc_efx/base/rhead_pci.c +++ b/drivers/common/sfc_efx/base/rhead_pci.c @@ -47,6 +47,7 @@ rhead_xilinx_cap_tbl_find_ef100_locator( __checkReturn efx_rc_t rhead_pci_nic_membar_lookup( __in efsys_pci_config_t *espcp, + __in const efx_pci_ops_t *epop, __out efx_bar_region_t *ebrp) { boolean_t xilinx_tbl_found = B_FALSE; @@ -65,7 +66,8 @@ rhead_pci_nic_membar_lookup( * the following discovery steps. */ while (1) { - rc = efx_pci_find_next_xilinx_cap_table(espcp, &pci_capa_offset, + rc = efx_pci_find_next_xilinx_cap_table(espcp, epop, + &pci_capa_offset, &xilinx_tbl_bar, &xilinx_tbl_offset); if (rc != 0) { @@ -90,7 +92,7 @@ rhead_pci_nic_membar_lookup( xilinx_tbl_found = B_TRUE; - EFSYS_PCI_FIND_MEM_BAR(espcp, xilinx_tbl_bar, &xil_eb, &rc); + rc = epop->epo_find_mem_bar(espcp, xilinx_tbl_bar, &xil_eb); if (rc != 0) goto fail2; @@ -110,7 +112,7 @@ rhead_pci_nic_membar_lookup( if (bar_found == B_FALSE) goto fail4; - EFSYS_PCI_FIND_MEM_BAR(espcp, ebrp->ebr_index, &nic_eb, &rc); + rc = epop->epo_find_mem_bar(espcp, ebrp->ebr_index, &nic_eb); if (rc != 0) goto fail5;