From patchwork Thu Sep 24 12:12:13 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Rybchenko X-Patchwork-Id: 78715 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id BB1FAA04B1; Thu, 24 Sep 2020 14:19:44 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id B5F7B1DEEF; Thu, 24 Sep 2020 14:13:58 +0200 (CEST) Received: from dispatch1-us1.ppe-hosted.com (dispatch1-us1.ppe-hosted.com [148.163.129.52]) by dpdk.org (Postfix) with ESMTP id A9DEF1DE1C for ; Thu, 24 Sep 2020 14:13:02 +0200 (CEST) Received: from mx1-us1.ppe-hosted.com (unknown [10.7.65.62]) by dispatch1-us1.ppe-hosted.com (PPE Hosted ESMTP Server) with ESMTP id 2487B60085 for ; Thu, 24 Sep 2020 12:13:02 +0000 (UTC) Received: from us4-mdac16-3.ut7.mdlocal (unknown [10.7.65.71]) by mx1-us1.ppe-hosted.com (PPE Hosted ESMTP Server) with ESMTP id 21C6F8009B for ; Thu, 24 Sep 2020 12:13:02 +0000 (UTC) X-Virus-Scanned: Proofpoint Essentials engine Received: from mx1-us1.ppe-hosted.com (unknown [10.7.65.174]) by mx1-us1.ppe-hosted.com (PPE Hosted ESMTP Server) with ESMTPS id 7B1AF280059 for ; Thu, 24 Sep 2020 12:13:01 +0000 (UTC) Received: from webmail.solarflare.com (uk.solarflare.com [193.34.186.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-SHA384 (256/256 bits)) (No client certificate requested) by mx1-us1.ppe-hosted.com (PPE Hosted ESMTP Server) with ESMTPS id 31D8B1C0064 for ; Thu, 24 Sep 2020 12:13:01 +0000 (UTC) Received: from ukex01.SolarFlarecom.com (10.17.10.4) by ukex01.SolarFlarecom.com (10.17.10.4) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 24 Sep 2020 13:12:47 +0100 Received: from opal.uk.solarflarecom.com (10.17.10.1) by ukex01.SolarFlarecom.com (10.17.10.4) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 24 Sep 2020 13:12:47 +0100 Received: from ukv-loginhost.uk.solarflarecom.com (ukv-loginhost.uk.solarflarecom.com [10.17.10.39]) by opal.uk.solarflarecom.com (8.13.8/8.13.8) with ESMTP id 08OCClN9026029; Thu, 24 Sep 2020 13:12:47 +0100 Received: from ukv-loginhost.uk.solarflarecom.com (localhost [127.0.0.1]) by ukv-loginhost.uk.solarflarecom.com (Postfix) with ESMTP id AA1C71613AB; Thu, 24 Sep 2020 13:12:47 +0100 (BST) From: Andrew Rybchenko To: CC: Ivan Malov Date: Thu, 24 Sep 2020 13:12:13 +0100 Message-ID: <1600949555-28043-39-git-send-email-arybchenko@solarflare.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1600949555-28043-1-git-send-email-arybchenko@solarflare.com> References: <1600764594-14752-1-git-send-email-arybchenko@solarflare.com> <1600949555-28043-1-git-send-email-arybchenko@solarflare.com> MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-12.5.0.1300-8.6.1012-25674.003 X-TM-AS-Result: No-12.470600-8.000000-10 X-TMASE-MatchedRID: lkU3smArgqHyZJjykKilZcdIMosX9xY4Dvc/j9oMIgXmWHHSYEnI8eZ5 Gn23AeDZuA9fFHhyLzywgcHDNo5AtCHhSBQfglfsA9lly13c/gGU1za3Jug9wh9W4auM/sn0+WA X4qDxTxHq0RAcFeb1OAHK23KfaC+PaqFV806Y13orV68vwQSkylM8G40owbvKpaH78JErK6OYpu G7kpoKR9YrQc5g34AdMVrs5lZbz83JvqS7wzm7XfKUR83BvqItdXSqvK7ZoGCdzjX37VUcWltoN q9iyPJtbAs8LS/YFkhTI/HRmiwtn28g58FzqzMmLIrMljt3advqobkz1A0A7RlsMW7N/z9acTUE eJCy7bvi8WK5PBuMtYAy6p60ZV62fJ5/bZ6npdg7AFczfjr/7BkSO4GwEnOICvhTBgm2UrZr7Wm 0sTFS1PctNx+suO4gtJ1tsSLpcfI= X-TM-AS-User-Approved-Sender: Yes X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--12.470600-8.000000 X-TMASE-Version: SMEX-12.5.0.1300-8.6.1012-25674.003 X-MDID: 1600949582-vARrd8xxOufB Subject: [dpdk-dev] [PATCH v3 38/60] common/sfc_efx/base: report restrictions for TSO version 3 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Ivan Malov Riverhead puts a number of restrictions on TSO transactions. Reflect some of them in the NIC configuration structure. Signed-off-by: Ivan Malov Signed-off-by: Andrew Rybchenko Reviewed-by: Andrew Lee Reviewed-by: Andy Moreton --- drivers/common/sfc_efx/base/ef10_nic.c | 21 +++++++++++++++++++++ drivers/common/sfc_efx/base/efx.h | 10 ++++++++++ drivers/common/sfc_efx/base/rhead_nic.c | 23 +++++++++++++++++++---- 3 files changed, 50 insertions(+), 4 deletions(-) diff --git a/drivers/common/sfc_efx/base/ef10_nic.c b/drivers/common/sfc_efx/base/ef10_nic.c index 43f3412f35..927af87e0d 100644 --- a/drivers/common/sfc_efx/base/ef10_nic.c +++ b/drivers/common/sfc_efx/base/ef10_nic.c @@ -2077,6 +2077,27 @@ ef10_nic_board_cfg( */ encp->enc_tx_tso_tcp_header_offset_limit = EF10_TCP_HEADER_OFFSET_LIMIT; + /* EF10 TSO engine demands that packet header be contiguous. */ + encp->enc_tx_tso_max_header_ndescs = 1; + + /* The overall TSO header length is not limited. */ + encp->enc_tx_tso_max_header_length = UINT32_MAX; + + /* + * There are no specific limitations on the number of + * TSO payload descriptors. + */ + encp->enc_tx_tso_max_payload_ndescs = UINT32_MAX; + + /* TSO superframe payload length is not limited. */ + encp->enc_tx_tso_max_payload_length = UINT32_MAX; + + /* + * Limitation on the maximum number of outgoing packets per + * TSO transaction described in SF-108452-SW. + */ + encp->enc_tx_tso_max_nframes = 32767; + /* * Set resource limits for MC_CMD_ALLOC_VIS. Note that we cannot use * MC_CMD_GET_RESOURCE_LIMITS here as that reports the available diff --git a/drivers/common/sfc_efx/base/efx.h b/drivers/common/sfc_efx/base/efx.h index 08f7cddc95..a2c2e49bba 100644 --- a/drivers/common/sfc_efx/base/efx.h +++ b/drivers/common/sfc_efx/base/efx.h @@ -1466,6 +1466,16 @@ typedef struct efx_nic_cfg_s { * the hardware to apply TSO packet edits. */ uint32_t enc_tx_tso_tcp_header_offset_limit; + /* Maximum number of header DMA descriptors per TSO transaction. */ + uint32_t enc_tx_tso_max_header_ndescs; + /* Maximum header length acceptable by TSO transaction. */ + uint32_t enc_tx_tso_max_header_length; + /* Maximum number of payload DMA descriptors per TSO transaction. */ + uint32_t enc_tx_tso_max_payload_ndescs; + /* Maximum payload length per TSO transaction. */ + uint32_t enc_tx_tso_max_payload_length; + /* Maximum number of frames to be generated per TSO transaction. */ + uint32_t enc_tx_tso_max_nframes; boolean_t enc_fw_assisted_tso_enabled; boolean_t enc_fw_assisted_tso_v2_enabled; boolean_t enc_fw_assisted_tso_v2_encap_enabled; diff --git a/drivers/common/sfc_efx/base/rhead_nic.c b/drivers/common/sfc_efx/base/rhead_nic.c index b779b4f8e1..7fb28eae31 100644 --- a/drivers/common/sfc_efx/base/rhead_nic.c +++ b/drivers/common/sfc_efx/base/rhead_nic.c @@ -33,11 +33,26 @@ rhead_board_cfg( encp->enc_tx_dma_desc_boundary = 0; /* - * Maximum number of bytes into the frame the TCP header can start for - * firmware assisted TSO to work. - * FIXME Get from design parameter DP_TSO_MAX_HDR_LEN. + * Initialise design parameters to either a runtime value read from + * the design parameters area or the well known default value + * (see SF-119689-TC section 4.4 for details). + * FIXME: Read design parameters area values. */ - encp->enc_tx_tso_tcp_header_offset_limit = 0; + encp->enc_tx_tso_max_header_ndescs = + ESE_EF100_DP_GZ_TSO_MAX_HDR_NUM_SEGS_DEFAULT; + encp->enc_tx_tso_max_header_length = + ESE_EF100_DP_GZ_TSO_MAX_HDR_LEN_DEFAULT; + encp->enc_tx_tso_max_payload_ndescs = + ESE_EF100_DP_GZ_TSO_MAX_PAYLOAD_NUM_SEGS_DEFAULT; + encp->enc_tx_tso_max_payload_length = + ESE_EF100_DP_GZ_TSO_MAX_PAYLOAD_LEN_DEFAULT; + encp->enc_tx_tso_max_nframes = + ESE_EF100_DP_GZ_TSO_MAX_NUM_FRAMES_DEFAULT; + + /* + * Riverhead does not put any restrictions on TCP header offset limit. + */ + encp->enc_tx_tso_tcp_header_offset_limit = UINT32_MAX; /* * Set resource limits for MC_CMD_ALLOC_VIS. Note that we cannot use