From patchwork Fri Sep 11 09:19:19 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Van Haaren, Harry" X-Patchwork-Id: 77369 Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 0E370A04B5; Fri, 11 Sep 2020 11:18:07 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 634691BFCD; Fri, 11 Sep 2020 11:18:06 +0200 (CEST) Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by dpdk.org (Postfix) with ESMTP id EFCD31BF90 for ; Fri, 11 Sep 2020 11:18:04 +0200 (CEST) IronPort-SDR: Lxu3LXCYp3THF+l4n+nf21aCW9Ls/Xr5MP7AHE2FBdGQT/1bVI66hGHdvw7L8z3TriZpydMZS0 nUfFLsjtKUNg== X-IronPort-AV: E=McAfee;i="6000,8403,9740"; a="156123284" X-IronPort-AV: E=Sophos;i="5.76,414,1592895600"; d="scan'208";a="156123284" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Sep 2020 02:18:03 -0700 IronPort-SDR: YzA9iw/RSDhWE2TDeY0/fdhfFO87nA7EzW/Mh8InOml2z48+irEAhLp7sbWnO8VJUwoPzRGYUh +g/H7JgmL6xQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.76,414,1592895600"; d="scan'208";a="300875657" Received: from silpixa00399779.ir.intel.com (HELO silpixa00399779.ger.corp.intel.com) ([10.237.222.209]) by orsmga003.jf.intel.com with ESMTP; 11 Sep 2020 02:18:02 -0700 From: Harry van Haaren To: dev@dpdk.org Cc: Harry van Haaren Date: Fri, 11 Sep 2020 10:19:19 +0100 Message-Id: <20200911091919.62167-1-harry.van.haaren@intel.com> X-Mailer: git-send-email 2.17.1 Subject: [dpdk-dev] [PATCH] eal: add new prefetch0_write variant X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This commit adds a new rte_prefetch0_write() variant, suggests to the compiler to use a prefetch instruction with intention to write. As a compiler builtin, the compiler can choose based on compilation target what the best implementation for this instruction is. Signed-off-by: Harry van Haaren --- The integer constants passed to the builtin are not available as a #define value, and doing #defines just for this write variant does not seems a nice solution to me... particularly for those using IDEs where any #define value is auto-hinted for code-completion. --- lib/librte_eal/include/generic/rte_prefetch.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/lib/librte_eal/include/generic/rte_prefetch.h b/lib/librte_eal/include/generic/rte_prefetch.h index 6e47bdfbad..44e2e9abfc 100644 --- a/lib/librte_eal/include/generic/rte_prefetch.h +++ b/lib/librte_eal/include/generic/rte_prefetch.h @@ -51,4 +51,20 @@ static inline void rte_prefetch2(const volatile void *p); */ static inline void rte_prefetch_non_temporal(const volatile void *p); +/** + * Prefetch a cache line into all cache levels, with intention to write. This + * prefetch variant hints to the CPU that the program is expecting to write to + * the cache line being prefetched. + * + * @param p Address to prefetch + */ +static inline void rte_prefetch0_write(const void *p) +{ + /* 1 indicates intention to write, 3 sets target cache level to L1. See + * GCC docs where these integer constants are described in more detail: + * https://gcc.gnu.org/onlinedocs/gcc/Other-Builtins.html + */ + __builtin_prefetch(p, 1, 3); +} + #endif /* _RTE_PREFETCH_H_ */