From patchwork Thu Sep 3 17:17:45 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hemant Agrawal X-Patchwork-Id: 76468 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 54054A04BF; Thu, 3 Sep 2020 19:24:08 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 8645A1C0CE; Thu, 3 Sep 2020 19:24:01 +0200 (CEST) Received: from inva020.nxp.com (inva020.nxp.com [92.121.34.13]) by dpdk.org (Postfix) with ESMTP id E6F4DE07 for ; Thu, 3 Sep 2020 19:23:59 +0200 (CEST) Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id C03F81A039B; Thu, 3 Sep 2020 19:23:59 +0200 (CEST) Received: from invc005.ap-rdc01.nxp.com (invc005.ap-rdc01.nxp.com [165.114.16.14]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id B190C1A023E; Thu, 3 Sep 2020 19:23:57 +0200 (CEST) Received: from bf-netperf1.ap.freescale.net (bf-netperf1.ap.freescale.net [10.232.133.63]) by invc005.ap-rdc01.nxp.com (Postfix) with ESMTP id A3E4A402F0; Thu, 3 Sep 2020 19:23:54 +0200 (CEST) From: Hemant Agrawal To: dev@dpdk.org Cc: akhil.goyal@nxp.com, Nipun Gupta , Hemant Agrawal Date: Thu, 3 Sep 2020 22:47:45 +0530 Message-Id: <20200903171745.13985-2-hemant.agrawal@nxp.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200903171745.13985-1-hemant.agrawal@nxp.com> References: <20200903171745.13985-1-hemant.agrawal@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Subject: [dpdk-dev] [PATCH 2/2] crypto/dpaa2_sec: support stats for secondary process X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" DPAA2 crypto object access need availability of MCP object pointer. In case of secondary process, we need to use local MCP pointer instead of primary process. Signed-off-by: Nipun Gupta Signed-off-by: Hemant Agrawal --- drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c b/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c index f480aafd0..14158a22d 100644 --- a/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c +++ b/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c @@ -3489,7 +3489,7 @@ void dpaa2_sec_stats_get(struct rte_cryptodev *dev, struct rte_cryptodev_stats *stats) { struct dpaa2_sec_dev_private *priv = dev->data->dev_private; - struct fsl_mc_io *dpseci = (struct fsl_mc_io *)priv->hw; + struct fsl_mc_io dpseci; struct dpseci_sec_counters counters = {0}; struct dpaa2_sec_qp **qp = (struct dpaa2_sec_qp **) dev->data->queue_pairs; @@ -3512,7 +3512,12 @@ void dpaa2_sec_stats_get(struct rte_cryptodev *dev, stats->dequeue_err_count += qp[i]->rx_vq.err_pkts; } - ret = dpseci_get_sec_counters(dpseci, CMD_PRI_LOW, priv->token, + /* In case as secondary process access stats, MCP portal in priv-hw + * may have primary process address. Need the secondary process + * based MCP portal address for this object. + */ + dpseci.regs = dpaa2_get_mcp_ptr(MC_PORTAL_INDEX); + ret = dpseci_get_sec_counters(&dpseci, CMD_PRI_LOW, priv->token, &counters); if (ret) { DPAA2_SEC_ERR("SEC counters failed");