vdpa/mlx5: fix completion queue assertion
diff mbox series

Message ID 1599035699-358487-1-git-send-email-matan@nvidia.com
State Accepted
Delegated to: Maxime Coquelin
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Series
  • vdpa/mlx5: fix completion queue assertion
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Commit Message

Matan Azrad Sept. 2, 2020, 8:34 a.m. UTC
The CQ configuration enables the collapse feature in HW what cause HW to
write all the completions in the first CQE.
When this feature is enabled the HW doesn't switch the owner bit when it
starts a new cycle of the CQ, not like working without the collapse
feature.

The current SW CQ polling wrongly added an assertion to validate the
owner bit switch what causes a panic in debug mode.

Remove the aforementioned assertion.

Fixes: c5f714e50b0e ("vdpa/mlx5: optimize completion queue poll")
Cc: stable@dpdk.org

Signed-off-by: Matan Azrad <matan@nvidia.com>
Acked-by: Xueming Li <xuemingl@nvidia.com>
---
 drivers/vdpa/mlx5/mlx5_vdpa_event.c | 2 --
 1 file changed, 2 deletions(-)

Comments

Maxime Coquelin Sept. 18, 2020, 10:33 a.m. UTC | #1
On 9/2/20 10:34 AM, Matan Azrad wrote:
> The CQ configuration enables the collapse feature in HW what cause HW to
> write all the completions in the first CQE.
> When this feature is enabled the HW doesn't switch the owner bit when it
> starts a new cycle of the CQ, not like working without the collapse
> feature.
> 
> The current SW CQ polling wrongly added an assertion to validate the
> owner bit switch what causes a panic in debug mode.
> 
> Remove the aforementioned assertion.
> 
> Fixes: c5f714e50b0e ("vdpa/mlx5: optimize completion queue poll")
> Cc: stable@dpdk.org
> 
> Signed-off-by: Matan Azrad <matan@nvidia.com>
> Acked-by: Xueming Li <xuemingl@nvidia.com>
> ---
>  drivers/vdpa/mlx5/mlx5_vdpa_event.c | 2 --
>  1 file changed, 2 deletions(-)
> 
> diff --git a/drivers/vdpa/mlx5/mlx5_vdpa_event.c b/drivers/vdpa/mlx5/mlx5_vdpa_event.c
> index 5a2d4fb..742ee62 100644
> --- a/drivers/vdpa/mlx5/mlx5_vdpa_event.c
> +++ b/drivers/vdpa/mlx5/mlx5_vdpa_event.c
> @@ -205,8 +205,6 @@
>  	comp = (cur_wqe_counter + 1u - next_wqe_counter) & cq_mask;
>  	if (comp) {
>  		cq->cq_ci += comp;
> -		MLX5_ASSERT(!!(cq->cq_ci & cq_size) ==
> -			    MLX5_CQE_OWNER(last_word.op_own));
>  		MLX5_ASSERT(MLX5_CQE_OPCODE(last_word.op_own) !=
>  			    MLX5_CQE_INVALID);
>  		if (unlikely(!(MLX5_CQE_OPCODE(last_word.op_own) ==
> 

Reviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>

Thanks,
Maxime
Maxime Coquelin Sept. 18, 2020, 12:29 p.m. UTC | #2
On 9/2/20 10:34 AM, Matan Azrad wrote:
> The CQ configuration enables the collapse feature in HW what cause HW to
> write all the completions in the first CQE.
> When this feature is enabled the HW doesn't switch the owner bit when it
> starts a new cycle of the CQ, not like working without the collapse
> feature.
> 
> The current SW CQ polling wrongly added an assertion to validate the
> owner bit switch what causes a panic in debug mode.
> 
> Remove the aforementioned assertion.
> 
> Fixes: c5f714e50b0e ("vdpa/mlx5: optimize completion queue poll")
> Cc: stable@dpdk.org
> 
> Signed-off-by: Matan Azrad <matan@nvidia.com>
> Acked-by: Xueming Li <xuemingl@nvidia.com>
> ---
>  drivers/vdpa/mlx5/mlx5_vdpa_event.c | 2 --
>  1 file changed, 2 deletions(-)

Applied to dpdk-next-virtio/master.

Thanks,
Maxime

Patch
diff mbox series

diff --git a/drivers/vdpa/mlx5/mlx5_vdpa_event.c b/drivers/vdpa/mlx5/mlx5_vdpa_event.c
index 5a2d4fb..742ee62 100644
--- a/drivers/vdpa/mlx5/mlx5_vdpa_event.c
+++ b/drivers/vdpa/mlx5/mlx5_vdpa_event.c
@@ -205,8 +205,6 @@ 
 	comp = (cur_wqe_counter + 1u - next_wqe_counter) & cq_mask;
 	if (comp) {
 		cq->cq_ci += comp;
-		MLX5_ASSERT(!!(cq->cq_ci & cq_size) ==
-			    MLX5_CQE_OWNER(last_word.op_own));
 		MLX5_ASSERT(MLX5_CQE_OPCODE(last_word.op_own) !=
 			    MLX5_CQE_INVALID);
 		if (unlikely(!(MLX5_CQE_OPCODE(last_word.op_own) ==