[1/4] common/octeontx2: add REE definitions and logging support
diff mbox series

Message ID 20200901122436.17748-2-guyk@marvell.com
State Superseded
Delegated to: Thomas Monjalon
Headers show
Series
  • Add Marvell OCTEON TX2 regex driver
Related show

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Context Check Description
ci/checkpatch warning coding style issues

Commit Message

Guy Kaneti Sept. 1, 2020, 12:24 p.m. UTC
From: Guy Kaneti <guyk@marvell.com>

Add REE mbox msg definitions, RVU and REE HW definitions

Signed-off-by: Guy Kaneti <guyk@marvell.com>
---
 drivers/common/octeontx2/hw/otx2_ree.h        |  27 +++++
 drivers/common/octeontx2/hw/otx2_rvu.h        |   5 +
 drivers/common/octeontx2/otx2_common.c        |   1 +
 drivers/common/octeontx2/otx2_common.h        |   5 +
 drivers/common/octeontx2/otx2_mbox.h          | 103 ++++++++++++++++++
 .../rte_common_octeontx2_version.map          |   1 +
 6 files changed, 142 insertions(+)
 create mode 100644 drivers/common/octeontx2/hw/otx2_ree.h

Comments

Liron Himi Oct. 11, 2020, 7:35 a.m. UTC | #1
Reviewed-by: Liron Himi <lironh@marvell.com>

-----Original Message-----
From: dev <dev-bounces@dpdk.org> On Behalf Of guyk@marvell.com
Sent: Tuesday, 1 September 2020 15:25
To: Jerin Jacob Kollanukkaran <jerinj@marvell.com>; Nithin Kumar Dabilpuram <ndabilpuram@marvell.com>; thomas@monjalon.net; mdr@ashroe.eu; nhorman@tuxdriver.com; bruce.richardson@intel.com; anatoly.burakov@intel.com; john.mcnamara@intel.com; marko.kovacevic@intel.com
Cc: dev@dpdk.org; Smadar Fuks <smadarf@marvell.com>; Dovrat Zifroni <dovrat@marvell.com>; Guy Kaneti <guyk@marvell.com>; orika@mellanox.com
Subject: [dpdk-dev] [PATCH 1/4] common/octeontx2: add REE definitions and logging support

From: Guy Kaneti <guyk@marvell.com>

Add REE mbox msg definitions, RVU and REE HW definitions

Signed-off-by: Guy Kaneti <guyk@marvell.com>
---
 drivers/common/octeontx2/hw/otx2_ree.h        |  27 +++++
 drivers/common/octeontx2/hw/otx2_rvu.h        |   5 +
 drivers/common/octeontx2/otx2_common.c        |   1 +
 drivers/common/octeontx2/otx2_common.h        |   5 +
 drivers/common/octeontx2/otx2_mbox.h          | 103 ++++++++++++++++++
 .../rte_common_octeontx2_version.map          |   1 +
 6 files changed, 142 insertions(+)
 create mode 100644 drivers/common/octeontx2/hw/otx2_ree.h

diff --git a/drivers/common/octeontx2/hw/otx2_ree.h b/drivers/common/octeontx2/hw/otx2_ree.h
new file mode 100644
index 000000000..b7481f125
--- /dev/null
+++ b/drivers/common/octeontx2/hw/otx2_ree.h
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright (C) 2020 Marvell International Ltd.
+ */
+
+#ifndef __OTX2_REE_HW_H__
+#define __OTX2_REE_HW_H__
+
+/* REE BAR0*/
+#define REE_AF_REEXM_MAX_MATCH		(0x80c8)
+
+/* REE BAR02 */
+#define REE_LF_MISC_INT                 (0x300)
+#define REE_LF_DONE_INT                 (0x120)
+
+#define REE_AF_QUEX_GMCTL(a)            (0x800 | (a) << 3)
+
+#define REE_AF_INT_VEC_RAS          (0x0ull)
+#define REE_AF_INT_VEC_RVU          (0x1ull)
+#define REE_AF_INT_VEC_QUE_DONE     (0x2ull)
+#define REE_AF_INT_VEC_AQ           (0x3ull)
+
+/* ENUMS */
+
+#define REE_LF_INT_VEC_QUE_DONE	(0x0ull)
+#define REE_LF_INT_VEC_MISC		(0x1ull)
+
+#endif /* __OTX2_REE_HW_H__*/
diff --git a/drivers/common/octeontx2/hw/otx2_rvu.h b/drivers/common/octeontx2/hw/otx2_rvu.h
index 330bfb37f..072515207 100644
--- a/drivers/common/octeontx2/hw/otx2_rvu.h
+++ b/drivers/common/octeontx2/hw/otx2_rvu.h
@@ -130,6 +130,7 @@
 #define RVU_BLOCK_TYPE_RAD                  (0xdull)
 #define RVU_BLOCK_TYPE_DFA                  (0xeull)
 #define RVU_BLOCK_TYPE_HNA                  (0xfull)
+#define RVU_BLOCK_TYPE_REE                  (0xeull)
 
 #define RVU_BLOCK_ADDR_RVUM                 (0x0ull)
 #define RVU_BLOCK_ADDR_LMT                  (0x1ull)
@@ -146,6 +147,8 @@
 #define RVU_BLOCK_ADDR_NDC2                 (0xeull)
 #define RVU_BLOCK_ADDR_R_END                (0x1full)
 #define RVU_BLOCK_ADDR_R_START              (0x14ull)
+#define RVU_BLOCK_ADDR_REE0                 (0x14ull)
+#define RVU_BLOCK_ADDR_REE1                 (0x15ull)
 
 #define RVU_VF_INT_VEC_MBOX                 (0x0ull)
 
@@ -167,6 +170,7 @@
 #define NPA_AF_BAR2_SEL			(0x9000000ull)
 #define CPT_AF_BAR2_SEL			(0x9000000ull)
 #define RVU_AF_BAR2_SEL			(0x9000000ull)
+#define REE_AF_BAR2_SEL			(0x9000000ull)
 
 #define AF_BAR2_ALIASX(a, b) \
 	(0x9100000ull | (uint64_t)(a) << 12 | (uint64_t)(b)) @@ -177,6 +181,7 @@
 #define NPA_AF_BAR2_ALIASX(a, b)		AF_BAR2_ALIASX(0, b)
 #define CPT_AF_BAR2_ALIASX(a, b)		AF_BAR2_ALIASX(a, b)
 #define RVU_AF_BAR2_ALIASX(a, b)		AF_BAR2_ALIASX(a, b)
+#define REE_AF_BAR2_ALIASX(a, b)		AF_BAR2_ALIASX(a, b)
 
 /* Structures definitions */
 
diff --git a/drivers/common/octeontx2/otx2_common.c b/drivers/common/octeontx2/otx2_common.c
index b292e999a..d23c50242 100644
--- a/drivers/common/octeontx2/otx2_common.c
+++ b/drivers/common/octeontx2/otx2_common.c
@@ -213,3 +213,4 @@ RTE_LOG_REGISTER(otx2_logtype_sso, pmd.event.octeontx2, NOTICE);  RTE_LOG_REGISTER(otx2_logtype_tim, pmd.event.octeontx2.timer, NOTICE);  RTE_LOG_REGISTER(otx2_logtype_dpi, pmd.raw.octeontx2.dpi, NOTICE);  RTE_LOG_REGISTER(otx2_logtype_ep, pmd.raw.octeontx2.ep, NOTICE);
+RTE_LOG_REGISTER(otx2_logtype_ree, pmd.regex.octeontx2, NOTICE);
diff --git a/drivers/common/octeontx2/otx2_common.h b/drivers/common/octeontx2/otx2_common.h
index 2168cde4d..b6779f710 100644
--- a/drivers/common/octeontx2/otx2_common.h
+++ b/drivers/common/octeontx2/otx2_common.h
@@ -21,6 +21,7 @@
 #include "hw/otx2_sso.h"
 #include "hw/otx2_ssow.h"
 #include "hw/otx2_tim.h"
+#include "hw/otx2_ree.h"
 
 /* Alignment */
 #define OTX2_ALIGN  128
@@ -96,6 +97,7 @@ extern int otx2_logtype_tm;  extern int otx2_logtype_tim;  extern int otx2_logtype_dpi;  extern int otx2_logtype_ep;
+extern int otx2_logtype_ree;
 
 #define otx2_err(fmt, args...)			\
 	RTE_LOG(ERR, PMD, "%s():%u " fmt "\n",	\
@@ -119,6 +121,7 @@ extern int otx2_logtype_ep;  #define otx2_tim_dbg(fmt, ...) otx2_dbg(tim, fmt, ##__VA_ARGS__)  #define otx2_dpi_dbg(fmt, ...) otx2_dbg(dpi, fmt, ##__VA_ARGS__)  #define otx2_sdp_dbg(fmt, ...) otx2_dbg(ep, fmt, ##__VA_ARGS__)
+#define otx2_ree_dbg(fmt, ...) otx2_dbg(ree, fmt, ##__VA_ARGS__)
 
 /* PCI IDs */
 #define PCI_VENDOR_ID_CAVIUM			0x177D
@@ -136,6 +139,8 @@ extern int otx2_logtype_ep;
 #define PCI_DEVID_OCTEONTX2_EP_VF		0xB203 /* OCTEON TX2 EP mode */
 #define PCI_DEVID_OCTEONTX2_RVU_SDP_PF		0xA0f6
 #define PCI_DEVID_OCTEONTX2_RVU_SDP_VF		0xA0f7
+#define PCI_DEVID_OCTEONTX2_RVU_REE_PF		0xA0f4
+#define PCI_DEVID_OCTEONTX2_RVU_REE_VF		0xA0f5
 
 /*
  * REVID for RVU PCIe devices.
diff --git a/drivers/common/octeontx2/otx2_mbox.h b/drivers/common/octeontx2/otx2_mbox.h
index 34b1d0663..b3c32e9a4 100644
--- a/drivers/common/octeontx2/otx2_mbox.h
+++ b/drivers/common/octeontx2/otx2_mbox.h
@@ -199,6 +199,19 @@ M(CPT_INLINE_IPSEC_CFG, 0xA04, cpt_inline_ipsec_cfg,			\
 M(CPT_RX_INLINE_LF_CFG, 0xBFE, cpt_rx_inline_lf_cfg,			\
 			       cpt_rx_inline_lf_cfg_msg, msg_rsp)	\
 M(CPT_GET_CAPS,		0xBFD, cpt_caps_get, msg_req, cpt_caps_rsp_msg)	\
+/* REE mbox IDs (range 0xE00 - 0xFFF) */				\
+M(REE_CONFIG_LF,	0xE01, ree_config_lf, ree_lf_req_msg,		\
+				msg_rsp)				\
+M(REE_RD_WR_REGISTER,	0xE02, ree_rd_wr_register, ree_rd_wr_reg_msg,	\
+				ree_rd_wr_reg_msg)			\
+M(REE_RULE_DB_PROG,	0xE03, ree_rule_db_prog,			\
+				ree_rule_db_prog_req_msg,		\
+				msg_rsp)				\
+M(REE_RULE_DB_LEN_GET,	0xE04, ree_rule_db_len_get, ree_req_msg,	\
+				ree_rule_db_len_rsp_msg)		\
+M(REE_RULE_DB_GET,	0xE05, ree_rule_db_get,				\
+				ree_rule_db_get_req_msg,		\
+				ree_rule_db_get_rsp_msg)		\
 /* NPC mbox IDs (range 0x6000 - 0x7FFF) */				\
 M(NPC_MCAM_ALLOC_ENTRY,	0x6000, npc_mcam_alloc_entry,			\
 				npc_mcam_alloc_entry_req,		\
@@ -1650,6 +1663,96 @@ struct tim_enable_rsp {
 	uint32_t __otx2_io currentbucket;
 };
 
+/* REE mailbox error codes
+ * Range 1001 - 1100.
+ */
+enum ree_af_status {
+	REE_AF_ERR_RULE_UNKNOWN_VALUE		= -1001,
+	REE_AF_ERR_LF_NO_MORE_RESOURCES		= -1002,
+	REE_AF_ERR_LF_INVALID			= -1003,
+	REE_AF_ERR_ACCESS_DENIED		= -1004,
+	REE_AF_ERR_RULE_DB_PARTIAL		= -1005,
+	REE_AF_ERR_RULE_DB_EQ_BAD_VALUE		= -1006,
+	REE_AF_ERR_RULE_DB_BLOCK_ALLOC_FAILED	= -1007,
+	REE_AF_ERR_BLOCK_NOT_IMPLEMENTED	= -1008,
+	REE_AF_ERR_RULE_DB_INC_OFFSET_TOO_BIG	= -1009,
+	REE_AF_ERR_RULE_DB_OFFSET_TOO_BIG	= -1010,
+	REE_AF_ERR_Q_IS_GRACEFUL_DIS		= -1011,
+	REE_AF_ERR_Q_NOT_GRACEFUL_DIS		= -1012,
+	REE_AF_ERR_RULE_DB_ALLOC_FAILED		= -1013,
+	REE_AF_ERR_RULE_DB_TOO_BIG		= -1014,
+	REE_AF_ERR_RULE_DB_GEQ_BAD_VALUE	= -1015,
+	REE_AF_ERR_RULE_DB_LEQ_BAD_VALUE	= -1016,
+	REE_AF_ERR_RULE_DB_WRONG_LENGTH		= -1017,
+	REE_AF_ERR_RULE_DB_WRONG_OFFSET		= -1018,
+	REE_AF_ERR_RULE_DB_BLOCK_TOO_BIG	= -1019,
+	REE_AF_ERR_RULE_DB_SHOULD_FILL_REQUEST	= -1020,
+	REE_AF_ERR_RULE_DBI_ALLOC_FAILED	= -1021,
+	REE_AF_ERR_LF_WRONG_PRIORITY		= -1022,
+	REE_AF_ERR_LF_SIZE_TOO_BIG		= -1023,
+};
+
+/* REE mbox message formats */
+
+struct ree_req_msg {
+	struct mbox_msghdr hdr;
+	uint32_t __otx2_io blkaddr;
+};
+
+struct ree_lf_req_msg {
+	struct mbox_msghdr hdr;
+	uint32_t __otx2_io blkaddr;
+	uint32_t __otx2_io size;
+	uint8_t __otx2_io lf;
+	uint8_t __otx2_io pri;
+};
+
+struct ree_rule_db_prog_req_msg {
+	struct mbox_msghdr hdr;
+#define REE_RULE_DB_REQ_BLOCK_SIZE (MBOX_SIZE >> 1)
+	uint8_t __otx2_io rule_db[REE_RULE_DB_REQ_BLOCK_SIZE];
+	uint32_t __otx2_io blkaddr; /* REE0 or REE1 */
+	uint32_t __otx2_io total_len; /* total len of rule db */
+	uint32_t __otx2_io offset; /* offset of current rule db block */
+	uint16_t __otx2_io len; /* length of rule db block */
+	uint8_t __otx2_io is_last; /* is this the last block */
+	uint8_t __otx2_io is_incremental; /* is incremental flow */
+	uint8_t __otx2_io is_dbi; /* is rule db incremental */ };
+
+struct ree_rule_db_get_req_msg {
+	struct mbox_msghdr hdr;
+	uint32_t __otx2_io blkaddr;
+	uint32_t __otx2_io offset; /* retrieve db from this offset */
+	uint8_t __otx2_io is_dbi; /* is request for rule db incremental */ };
+
+struct ree_rd_wr_reg_msg {
+	struct mbox_msghdr hdr;
+	uint64_t __otx2_io reg_offset;
+	uint64_t __otx2_io *ret_val;
+	uint64_t __otx2_io val;
+	uint32_t __otx2_io blkaddr;
+	uint8_t __otx2_io is_write;
+};
+
+struct ree_rule_db_len_rsp_msg {
+	struct mbox_msghdr hdr;
+	uint32_t __otx2_io blkaddr;
+	uint32_t __otx2_io len;
+	uint32_t __otx2_io inc_len;
+};
+
+struct ree_rule_db_get_rsp_msg {
+	struct mbox_msghdr hdr;
+#define REE_RULE_DB_RSP_BLOCK_SIZE (MBOX_DOWN_TX_SIZE - SZ_1K)
+	uint8_t __otx2_io rule_db[REE_RULE_DB_RSP_BLOCK_SIZE];
+	uint32_t __otx2_io total_len; /* total len of rule db */
+	uint32_t __otx2_io offset; /* offset of current rule db block */
+	uint16_t __otx2_io len; /* length of rule db block */
+	uint8_t __otx2_io is_last; /* is this the last block */ };
+
 __rte_internal
 const char *otx2_mbox_id2name(uint16_t id);  int otx2_mbox_id2size(uint16_t id); diff --git a/drivers/common/octeontx2/rte_common_octeontx2_version.map b/drivers/common/octeontx2/rte_common_octeontx2_version.map
index 9a9969613..d269d70d8 100644
--- a/drivers/common/octeontx2/rte_common_octeontx2_version.map
+++ b/drivers/common/octeontx2/rte_common_octeontx2_version.map
@@ -38,6 +38,7 @@ INTERNAL {
 	otx2_sso_pf_func_get;
 	otx2_sso_pf_func_set;
 	otx2_unregister_irq;
+	otx2_logtype_ree;
 
 	local: *;
 };
--
2.28.0

Patch
diff mbox series

diff --git a/drivers/common/octeontx2/hw/otx2_ree.h b/drivers/common/octeontx2/hw/otx2_ree.h
new file mode 100644
index 000000000..b7481f125
--- /dev/null
+++ b/drivers/common/octeontx2/hw/otx2_ree.h
@@ -0,0 +1,27 @@ 
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright (C) 2020 Marvell International Ltd.
+ */
+
+#ifndef __OTX2_REE_HW_H__
+#define __OTX2_REE_HW_H__
+
+/* REE BAR0*/
+#define REE_AF_REEXM_MAX_MATCH		(0x80c8)
+
+/* REE BAR02 */
+#define REE_LF_MISC_INT                 (0x300)
+#define REE_LF_DONE_INT                 (0x120)
+
+#define REE_AF_QUEX_GMCTL(a)            (0x800 | (a) << 3)
+
+#define REE_AF_INT_VEC_RAS          (0x0ull)
+#define REE_AF_INT_VEC_RVU          (0x1ull)
+#define REE_AF_INT_VEC_QUE_DONE     (0x2ull)
+#define REE_AF_INT_VEC_AQ           (0x3ull)
+
+/* ENUMS */
+
+#define REE_LF_INT_VEC_QUE_DONE	(0x0ull)
+#define REE_LF_INT_VEC_MISC		(0x1ull)
+
+#endif /* __OTX2_REE_HW_H__*/
diff --git a/drivers/common/octeontx2/hw/otx2_rvu.h b/drivers/common/octeontx2/hw/otx2_rvu.h
index 330bfb37f..072515207 100644
--- a/drivers/common/octeontx2/hw/otx2_rvu.h
+++ b/drivers/common/octeontx2/hw/otx2_rvu.h
@@ -130,6 +130,7 @@ 
 #define RVU_BLOCK_TYPE_RAD                  (0xdull)
 #define RVU_BLOCK_TYPE_DFA                  (0xeull)
 #define RVU_BLOCK_TYPE_HNA                  (0xfull)
+#define RVU_BLOCK_TYPE_REE                  (0xeull)
 
 #define RVU_BLOCK_ADDR_RVUM                 (0x0ull)
 #define RVU_BLOCK_ADDR_LMT                  (0x1ull)
@@ -146,6 +147,8 @@ 
 #define RVU_BLOCK_ADDR_NDC2                 (0xeull)
 #define RVU_BLOCK_ADDR_R_END                (0x1full)
 #define RVU_BLOCK_ADDR_R_START              (0x14ull)
+#define RVU_BLOCK_ADDR_REE0                 (0x14ull)
+#define RVU_BLOCK_ADDR_REE1                 (0x15ull)
 
 #define RVU_VF_INT_VEC_MBOX                 (0x0ull)
 
@@ -167,6 +170,7 @@ 
 #define NPA_AF_BAR2_SEL			(0x9000000ull)
 #define CPT_AF_BAR2_SEL			(0x9000000ull)
 #define RVU_AF_BAR2_SEL			(0x9000000ull)
+#define REE_AF_BAR2_SEL			(0x9000000ull)
 
 #define AF_BAR2_ALIASX(a, b) \
 	(0x9100000ull | (uint64_t)(a) << 12 | (uint64_t)(b))
@@ -177,6 +181,7 @@ 
 #define NPA_AF_BAR2_ALIASX(a, b)		AF_BAR2_ALIASX(0, b)
 #define CPT_AF_BAR2_ALIASX(a, b)		AF_BAR2_ALIASX(a, b)
 #define RVU_AF_BAR2_ALIASX(a, b)		AF_BAR2_ALIASX(a, b)
+#define REE_AF_BAR2_ALIASX(a, b)		AF_BAR2_ALIASX(a, b)
 
 /* Structures definitions */
 
diff --git a/drivers/common/octeontx2/otx2_common.c b/drivers/common/octeontx2/otx2_common.c
index b292e999a..d23c50242 100644
--- a/drivers/common/octeontx2/otx2_common.c
+++ b/drivers/common/octeontx2/otx2_common.c
@@ -213,3 +213,4 @@  RTE_LOG_REGISTER(otx2_logtype_sso, pmd.event.octeontx2, NOTICE);
 RTE_LOG_REGISTER(otx2_logtype_tim, pmd.event.octeontx2.timer, NOTICE);
 RTE_LOG_REGISTER(otx2_logtype_dpi, pmd.raw.octeontx2.dpi, NOTICE);
 RTE_LOG_REGISTER(otx2_logtype_ep, pmd.raw.octeontx2.ep, NOTICE);
+RTE_LOG_REGISTER(otx2_logtype_ree, pmd.regex.octeontx2, NOTICE);
diff --git a/drivers/common/octeontx2/otx2_common.h b/drivers/common/octeontx2/otx2_common.h
index 2168cde4d..b6779f710 100644
--- a/drivers/common/octeontx2/otx2_common.h
+++ b/drivers/common/octeontx2/otx2_common.h
@@ -21,6 +21,7 @@ 
 #include "hw/otx2_sso.h"
 #include "hw/otx2_ssow.h"
 #include "hw/otx2_tim.h"
+#include "hw/otx2_ree.h"
 
 /* Alignment */
 #define OTX2_ALIGN  128
@@ -96,6 +97,7 @@  extern int otx2_logtype_tm;
 extern int otx2_logtype_tim;
 extern int otx2_logtype_dpi;
 extern int otx2_logtype_ep;
+extern int otx2_logtype_ree;
 
 #define otx2_err(fmt, args...)			\
 	RTE_LOG(ERR, PMD, "%s():%u " fmt "\n",	\
@@ -119,6 +121,7 @@  extern int otx2_logtype_ep;
 #define otx2_tim_dbg(fmt, ...) otx2_dbg(tim, fmt, ##__VA_ARGS__)
 #define otx2_dpi_dbg(fmt, ...) otx2_dbg(dpi, fmt, ##__VA_ARGS__)
 #define otx2_sdp_dbg(fmt, ...) otx2_dbg(ep, fmt, ##__VA_ARGS__)
+#define otx2_ree_dbg(fmt, ...) otx2_dbg(ree, fmt, ##__VA_ARGS__)
 
 /* PCI IDs */
 #define PCI_VENDOR_ID_CAVIUM			0x177D
@@ -136,6 +139,8 @@  extern int otx2_logtype_ep;
 #define PCI_DEVID_OCTEONTX2_EP_VF		0xB203 /* OCTEON TX2 EP mode */
 #define PCI_DEVID_OCTEONTX2_RVU_SDP_PF		0xA0f6
 #define PCI_DEVID_OCTEONTX2_RVU_SDP_VF		0xA0f7
+#define PCI_DEVID_OCTEONTX2_RVU_REE_PF		0xA0f4
+#define PCI_DEVID_OCTEONTX2_RVU_REE_VF		0xA0f5
 
 /*
  * REVID for RVU PCIe devices.
diff --git a/drivers/common/octeontx2/otx2_mbox.h b/drivers/common/octeontx2/otx2_mbox.h
index 34b1d0663..b3c32e9a4 100644
--- a/drivers/common/octeontx2/otx2_mbox.h
+++ b/drivers/common/octeontx2/otx2_mbox.h
@@ -199,6 +199,19 @@  M(CPT_INLINE_IPSEC_CFG, 0xA04, cpt_inline_ipsec_cfg,			\
 M(CPT_RX_INLINE_LF_CFG, 0xBFE, cpt_rx_inline_lf_cfg,			\
 			       cpt_rx_inline_lf_cfg_msg, msg_rsp)	\
 M(CPT_GET_CAPS,		0xBFD, cpt_caps_get, msg_req, cpt_caps_rsp_msg)	\
+/* REE mbox IDs (range 0xE00 - 0xFFF) */				\
+M(REE_CONFIG_LF,	0xE01, ree_config_lf, ree_lf_req_msg,		\
+				msg_rsp)				\
+M(REE_RD_WR_REGISTER,	0xE02, ree_rd_wr_register, ree_rd_wr_reg_msg,	\
+				ree_rd_wr_reg_msg)			\
+M(REE_RULE_DB_PROG,	0xE03, ree_rule_db_prog,			\
+				ree_rule_db_prog_req_msg,		\
+				msg_rsp)				\
+M(REE_RULE_DB_LEN_GET,	0xE04, ree_rule_db_len_get, ree_req_msg,	\
+				ree_rule_db_len_rsp_msg)		\
+M(REE_RULE_DB_GET,	0xE05, ree_rule_db_get,				\
+				ree_rule_db_get_req_msg,		\
+				ree_rule_db_get_rsp_msg)		\
 /* NPC mbox IDs (range 0x6000 - 0x7FFF) */				\
 M(NPC_MCAM_ALLOC_ENTRY,	0x6000, npc_mcam_alloc_entry,			\
 				npc_mcam_alloc_entry_req,		\
@@ -1650,6 +1663,96 @@  struct tim_enable_rsp {
 	uint32_t __otx2_io currentbucket;
 };
 
+/* REE mailbox error codes
+ * Range 1001 - 1100.
+ */
+enum ree_af_status {
+	REE_AF_ERR_RULE_UNKNOWN_VALUE		= -1001,
+	REE_AF_ERR_LF_NO_MORE_RESOURCES		= -1002,
+	REE_AF_ERR_LF_INVALID			= -1003,
+	REE_AF_ERR_ACCESS_DENIED		= -1004,
+	REE_AF_ERR_RULE_DB_PARTIAL		= -1005,
+	REE_AF_ERR_RULE_DB_EQ_BAD_VALUE		= -1006,
+	REE_AF_ERR_RULE_DB_BLOCK_ALLOC_FAILED	= -1007,
+	REE_AF_ERR_BLOCK_NOT_IMPLEMENTED	= -1008,
+	REE_AF_ERR_RULE_DB_INC_OFFSET_TOO_BIG	= -1009,
+	REE_AF_ERR_RULE_DB_OFFSET_TOO_BIG	= -1010,
+	REE_AF_ERR_Q_IS_GRACEFUL_DIS		= -1011,
+	REE_AF_ERR_Q_NOT_GRACEFUL_DIS		= -1012,
+	REE_AF_ERR_RULE_DB_ALLOC_FAILED		= -1013,
+	REE_AF_ERR_RULE_DB_TOO_BIG		= -1014,
+	REE_AF_ERR_RULE_DB_GEQ_BAD_VALUE	= -1015,
+	REE_AF_ERR_RULE_DB_LEQ_BAD_VALUE	= -1016,
+	REE_AF_ERR_RULE_DB_WRONG_LENGTH		= -1017,
+	REE_AF_ERR_RULE_DB_WRONG_OFFSET		= -1018,
+	REE_AF_ERR_RULE_DB_BLOCK_TOO_BIG	= -1019,
+	REE_AF_ERR_RULE_DB_SHOULD_FILL_REQUEST	= -1020,
+	REE_AF_ERR_RULE_DBI_ALLOC_FAILED	= -1021,
+	REE_AF_ERR_LF_WRONG_PRIORITY		= -1022,
+	REE_AF_ERR_LF_SIZE_TOO_BIG		= -1023,
+};
+
+/* REE mbox message formats */
+
+struct ree_req_msg {
+	struct mbox_msghdr hdr;
+	uint32_t __otx2_io blkaddr;
+};
+
+struct ree_lf_req_msg {
+	struct mbox_msghdr hdr;
+	uint32_t __otx2_io blkaddr;
+	uint32_t __otx2_io size;
+	uint8_t __otx2_io lf;
+	uint8_t __otx2_io pri;
+};
+
+struct ree_rule_db_prog_req_msg {
+	struct mbox_msghdr hdr;
+#define REE_RULE_DB_REQ_BLOCK_SIZE (MBOX_SIZE >> 1)
+	uint8_t __otx2_io rule_db[REE_RULE_DB_REQ_BLOCK_SIZE];
+	uint32_t __otx2_io blkaddr; /* REE0 or REE1 */
+	uint32_t __otx2_io total_len; /* total len of rule db */
+	uint32_t __otx2_io offset; /* offset of current rule db block */
+	uint16_t __otx2_io len; /* length of rule db block */
+	uint8_t __otx2_io is_last; /* is this the last block */
+	uint8_t __otx2_io is_incremental; /* is incremental flow */
+	uint8_t __otx2_io is_dbi; /* is rule db incremental */
+};
+
+struct ree_rule_db_get_req_msg {
+	struct mbox_msghdr hdr;
+	uint32_t __otx2_io blkaddr;
+	uint32_t __otx2_io offset; /* retrieve db from this offset */
+	uint8_t __otx2_io is_dbi; /* is request for rule db incremental */
+};
+
+struct ree_rd_wr_reg_msg {
+	struct mbox_msghdr hdr;
+	uint64_t __otx2_io reg_offset;
+	uint64_t __otx2_io *ret_val;
+	uint64_t __otx2_io val;
+	uint32_t __otx2_io blkaddr;
+	uint8_t __otx2_io is_write;
+};
+
+struct ree_rule_db_len_rsp_msg {
+	struct mbox_msghdr hdr;
+	uint32_t __otx2_io blkaddr;
+	uint32_t __otx2_io len;
+	uint32_t __otx2_io inc_len;
+};
+
+struct ree_rule_db_get_rsp_msg {
+	struct mbox_msghdr hdr;
+#define REE_RULE_DB_RSP_BLOCK_SIZE (MBOX_DOWN_TX_SIZE - SZ_1K)
+	uint8_t __otx2_io rule_db[REE_RULE_DB_RSP_BLOCK_SIZE];
+	uint32_t __otx2_io total_len; /* total len of rule db */
+	uint32_t __otx2_io offset; /* offset of current rule db block */
+	uint16_t __otx2_io len; /* length of rule db block */
+	uint8_t __otx2_io is_last; /* is this the last block */
+};
+
 __rte_internal
 const char *otx2_mbox_id2name(uint16_t id);
 int otx2_mbox_id2size(uint16_t id);
diff --git a/drivers/common/octeontx2/rte_common_octeontx2_version.map b/drivers/common/octeontx2/rte_common_octeontx2_version.map
index 9a9969613..d269d70d8 100644
--- a/drivers/common/octeontx2/rte_common_octeontx2_version.map
+++ b/drivers/common/octeontx2/rte_common_octeontx2_version.map
@@ -38,6 +38,7 @@  INTERNAL {
 	otx2_sso_pf_func_get;
 	otx2_sso_pf_func_set;
 	otx2_unregister_irq;
+	otx2_logtype_ree;
 
 	local: *;
 };