[v7,3/4] common/qat: use WC store to update queue tail registers
diff mbox series

Message ID 1594902556-19511-4-git-send-email-radu.nicolau@intel.com
State Superseded
Delegated to: David Marchand
Headers show
Series
  • eal: add WC store functions
Related show

Checks

Context Check Description
ci/Intel-compilation success Compilation OK
ci/checkpatch success coding style OK

Commit Message

Radu Nicolau July 16, 2020, 12:29 p.m. UTC
Performance improvement: use a write combining store
instead of a regular mmio write to update queue tail
registers.

Signed-off-by: Radu Nicolau <radu.nicolau@intel.com>
---
 drivers/common/qat/qat_adf/adf_transport_access_macros.h | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

Patch
diff mbox series

diff --git a/drivers/common/qat/qat_adf/adf_transport_access_macros.h b/drivers/common/qat/qat_adf/adf_transport_access_macros.h
index 1eef551..504ffb7 100644
--- a/drivers/common/qat/qat_adf/adf_transport_access_macros.h
+++ b/drivers/common/qat/qat_adf/adf_transport_access_macros.h
@@ -9,6 +9,8 @@ 
 /* CSR write macro */
 #define ADF_CSR_WR(csrAddr, csrOffset, val)		\
 	rte_write32(val, (((uint8_t *)csrAddr) + csrOffset))
+#define ADF_CSR_WC_WR(csrAddr, csrOffset, val)		\
+	rte_write32_wc(val, (((uint8_t *)csrAddr) + csrOffset))
 
 /* CSR read macro */
 #define ADF_CSR_RD(csrAddr, csrOffset)			\
@@ -110,10 +112,10 @@  do { \
 		ADF_RING_CSR_RING_UBASE + (ring << 2), u_base);	\
 } while (0)
 #define WRITE_CSR_RING_HEAD(csr_base_addr, bank, ring, value) \
-	ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
+	ADF_CSR_WC_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
 		ADF_RING_CSR_RING_HEAD + (ring << 2), value)
 #define WRITE_CSR_RING_TAIL(csr_base_addr, bank, ring, value) \
-	ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
+	ADF_CSR_WC_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
 		ADF_RING_CSR_RING_TAIL + (ring << 2), value)
 #define WRITE_CSR_INT_SRCSEL(csr_base_addr, bank) \
 do { \