From patchwork Thu Jul 16 08:39:27 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tejasree Kondoj X-Patchwork-Id: 74184 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id AB8B7A0546; Thu, 16 Jul 2020 09:45:56 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 9D2F21BEB2; Thu, 16 Jul 2020 09:45:49 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by dpdk.org (Postfix) with ESMTP id 325AD4F9A for ; Thu, 16 Jul 2020 09:45:48 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 06G7YjkK004484; Thu, 16 Jul 2020 00:45:47 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0818; bh=owoKJPQzIiw4SfZLF4/r8sBqoHnLCBcpfSc2m49RVto=; b=UZt2Z7TvBHA+QOvO30xf7UQ6AncbUv/AZK56+Ns34YPAb1juenX2Me/2tPgG2IOQPr5y cNc65+EHQrhkZiSnkTIKRNYff94shT+2H77pURAdpBuQ0joh9nOpi/NXoJQAdcBVTNRH hERsdJTyYlWqtn71swXvnioiQKwvJKTFHCsYqVoSmRxt01X4BKiq2iOVuL34lomxZ2yh ryzXZAIBPrstfTaDYls0wzVkQ1W8hGu+5LmrQevBJw5xXA3wKhx4amC3i4lcE3j51LvF H1cUHO+JFatWOi7zqW96OkhEGEzmIrZvPDC1g0zFW/NXhww9IKX4oXkWOH88Xuvep1ze KA== Received: from sc-exch01.marvell.com ([199.233.58.181]) by mx0b-0016f401.pphosted.com with ESMTP id 328mmhxm89-2 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Thu, 16 Jul 2020 00:45:47 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by SC-EXCH01.marvell.com (10.93.176.81) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 16 Jul 2020 00:45:45 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 16 Jul 2020 00:45:46 -0700 Received: from hyd1554T5810.caveonetworks.com.com (unknown [10.29.57.11]) by maili.marvell.com (Postfix) with ESMTP id A35223F7041; Thu, 16 Jul 2020 00:45:43 -0700 (PDT) From: Tejasree Kondoj To: Akhil Goyal , Radu Nicolau CC: Tejasree Kondoj , Narayana Prasad , Anoob Joseph , Vamsi Attunuru , Date: Thu, 16 Jul 2020 14:09:27 +0530 Message-ID: <20200716083931.29092-5-ktejasree@marvell.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200716083931.29092-1-ktejasree@marvell.com> References: <20200716083931.29092-1-ktejasree@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235, 18.0.687 definitions=2020-07-16_04:2020-07-16, 2020-07-16 signatures=0 Subject: [dpdk-dev] [PATCH v3 4/8] crypto/octeontx2: add cryptodev sec registration X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This patch registers security operations with cryptodev. Signed-off-by: Vamsi Attunuru Signed-off-by: Tejasree Kondoj --- doc/guides/cryptodevs/features/octeontx2.ini | 1 + drivers/crypto/octeontx2/Makefile | 1 + drivers/crypto/octeontx2/meson.build | 3 +- drivers/crypto/octeontx2/otx2_cryptodev.c | 12 ++++- drivers/crypto/octeontx2/otx2_cryptodev_sec.c | 46 +++++++++++++++++++ drivers/crypto/octeontx2/otx2_cryptodev_sec.h | 6 +++ 6 files changed, 67 insertions(+), 2 deletions(-) create mode 100644 drivers/crypto/octeontx2/otx2_cryptodev_sec.c diff --git a/doc/guides/cryptodevs/features/octeontx2.ini b/doc/guides/cryptodevs/features/octeontx2.ini index e865466b8c..c7e418d826 100644 --- a/doc/guides/cryptodevs/features/octeontx2.ini +++ b/doc/guides/cryptodevs/features/octeontx2.ini @@ -8,6 +8,7 @@ Symmetric crypto = Y Asymmetric crypto = Y Sym operation chaining = Y HW Accelerated = Y +Protocol offload = Y In Place SGL = Y OOP SGL In LB Out = Y OOP SGL In SGL Out = Y diff --git a/drivers/crypto/octeontx2/Makefile b/drivers/crypto/octeontx2/Makefile index 5f9a6a0e3f..14152c6117 100644 --- a/drivers/crypto/octeontx2/Makefile +++ b/drivers/crypto/octeontx2/Makefile @@ -38,6 +38,7 @@ SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO) += otx2_cryptodev_capabilities.c SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO) += otx2_cryptodev_hw_access.c SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO) += otx2_cryptodev_mbox.c SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO) += otx2_cryptodev_ops.c +SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO) += otx2_cryptodev_sec.c # export include files SYMLINK-y-include += diff --git a/drivers/crypto/octeontx2/meson.build b/drivers/crypto/octeontx2/meson.build index 0948e73607..148ec184a6 100644 --- a/drivers/crypto/octeontx2/meson.build +++ b/drivers/crypto/octeontx2/meson.build @@ -17,7 +17,8 @@ sources = files('otx2_cryptodev.c', 'otx2_cryptodev_capabilities.c', 'otx2_cryptodev_hw_access.c', 'otx2_cryptodev_mbox.c', - 'otx2_cryptodev_ops.c') + 'otx2_cryptodev_ops.c', + 'otx2_cryptodev_sec.c') extra_flags = [] # This integrated controller runs only on a arm64 machine, remove 32bit warnings diff --git a/drivers/crypto/octeontx2/otx2_cryptodev.c b/drivers/crypto/octeontx2/otx2_cryptodev.c index a51d532553..e9b7c1cc04 100644 --- a/drivers/crypto/octeontx2/otx2_cryptodev.c +++ b/drivers/crypto/octeontx2/otx2_cryptodev.c @@ -17,6 +17,7 @@ #include "otx2_cryptodev_capabilities.h" #include "otx2_cryptodev_mbox.h" #include "otx2_cryptodev_ops.h" +#include "otx2_cryptodev_sec.h" #include "otx2_dev.h" /* CPT common headers */ @@ -103,6 +104,11 @@ otx2_cpt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, otx2_crypto_capabilities_init(vf->hw_caps); + /* Create security ctx */ + ret = otx2_crypto_sec_ctx_create(dev); + if (ret) + goto otx2_dev_fini; + dev->feature_flags = RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO | RTE_CRYPTODEV_FF_HW_ACCELERATED | RTE_CRYPTODEV_FF_SYM_OPERATION_CHAINING | @@ -111,7 +117,8 @@ otx2_cpt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, RTE_CRYPTODEV_FF_OOP_SGL_IN_SGL_OUT | RTE_CRYPTODEV_FF_ASYMMETRIC_CRYPTO | RTE_CRYPTODEV_FF_RSA_PRIV_OP_KEY_QT | - RTE_CRYPTODEV_FF_SYM_SESSIONLESS; + RTE_CRYPTODEV_FF_SYM_SESSIONLESS | + RTE_CRYPTODEV_FF_SECURITY; return 0; @@ -140,6 +147,9 @@ otx2_cpt_pci_remove(struct rte_pci_device *pci_dev) if (dev == NULL) return -ENODEV; + /* Destroy security ctx */ + otx2_crypto_sec_ctx_destroy(dev); + return rte_cryptodev_pmd_destroy(dev); } diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_sec.c b/drivers/crypto/octeontx2/otx2_cryptodev_sec.c new file mode 100644 index 0000000000..d937e6f37a --- /dev/null +++ b/drivers/crypto/octeontx2/otx2_cryptodev_sec.c @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright (C) 2020 Marvell International Ltd. + */ + +#include +#include +#include +#include + +#include "otx2_cryptodev_sec.h" + +static struct rte_security_ops otx2_crypto_sec_ops = { + .session_create = NULL, + .session_destroy = NULL, + .session_get_size = NULL, + .set_pkt_metadata = NULL, + .get_userdata = NULL, + .capabilities_get = NULL +}; + +int +otx2_crypto_sec_ctx_create(struct rte_cryptodev *cdev) +{ + struct rte_security_ctx *ctx; + + ctx = rte_malloc("otx2_cpt_dev_sec_ctx", + sizeof(struct rte_security_ctx), 0); + + if (ctx == NULL) + return -ENOMEM; + + /* Populate ctx */ + ctx->device = cdev; + ctx->ops = &otx2_crypto_sec_ops; + ctx->sess_cnt = 0; + + cdev->security_ctx = ctx; + + return 0; +} + +void +otx2_crypto_sec_ctx_destroy(struct rte_cryptodev *cdev) +{ + rte_free(cdev->security_ctx); +} diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_sec.h b/drivers/crypto/octeontx2/otx2_cryptodev_sec.h index 253f62d873..b989251e71 100644 --- a/drivers/crypto/octeontx2/otx2_cryptodev_sec.h +++ b/drivers/crypto/octeontx2/otx2_cryptodev_sec.h @@ -5,6 +5,8 @@ #ifndef __OTX2_CRYPTODEV_SEC_H__ #define __OTX2_CRYPTODEV_SEC_H__ +#include + #include "otx2_ipsec_po.h" struct otx2_sec_session_ipsec_lp { @@ -55,4 +57,8 @@ struct otx2_sec_session_ipsec_lp { uint8_t auth_iv_length; }; +int otx2_crypto_sec_ctx_create(struct rte_cryptodev *crypto_dev); + +void otx2_crypto_sec_ctx_destroy(struct rte_cryptodev *crypto_dev); + #endif /* __OTX2_CRYPTODEV_SEC_H__ */