[2/5] net/mlx5: add flow translation of eCPRI header
diff mbox series

Message ID 1594219387-240274-3-git-send-email-bingz@mellanox.com
State Superseded, archived
Delegated to: Raslan Darawsheh
Headers show
Series
  • add eCPRI support in mlx5 driver
Related show

Checks

Context Check Description
ci/Intel-compilation success Compilation OK
ci/checkpatch warning coding style issues

Commit Message

Bing Zhao July 8, 2020, 2:43 p.m. UTC
In the translation stage, the eCPRI item should be translated into
the format that lower layer driver could use. All the fields that
need to matched must be in network byte order after translation, as
well as the mask. Since the header in the item belongs to the network
layers stack, and the input parameter of the header is considered to
be in big-endian format already.

Base on the definition in the PRM, the DW samples will be used for
matching in the FTE/STE. Now, the type field and only the PC ID, RTC
ID, and DLY MSR ID of the payload will be supported. The masks should
be 00 ff 00 00 ff ff(00) 00 00 in the network order. Two DWs are
needed to support such matching. The mask fields could be zeros to
support some wildcard rules. But it makes no sense to support the
rule matching only on the payload but without matching type filed.

The DW samples should be stored after the flex parser creation for
eCPRI. There is no need to query the sample IDs each time when
creating a flow rule with eCPRI item. It will not introduce
insertion rate degradation significantly.

Signed-off-by: Bing Zhao <bingz@mellanox.com>
---
 drivers/common/mlx5/mlx5_prm.h  |  16 ++++-
 drivers/net/mlx5/mlx5.h         |  15 +++++
 drivers/net/mlx5/mlx5_flow_dv.c | 130 ++++++++++++++++++++++++++++++++++++++++
 3 files changed, 160 insertions(+), 1 deletion(-)

Comments

Thomas Monjalon July 9, 2020, 12:22 p.m. UTC | #1
08/07/2020 16:43, Bing Zhao:
> In the translation stage, the eCPRI item should be translated into
> the format that lower layer driver could use. All the fields that
> need to matched must be in network byte order after translation, as
> well as the mask. Since the header in the item belongs to the network
> layers stack, and the input parameter of the header is considered to
> be in big-endian format already.
> 
> Base on the definition in the PRM, the DW samples will be used for
> matching in the FTE/STE. Now, the type field and only the PC ID, RTC
> ID, and DLY MSR ID of the payload will be supported. The masks should
> be 00 ff 00 00 ff ff(00) 00 00 in the network order. Two DWs are
> needed to support such matching. The mask fields could be zeros to
> support some wildcard rules. But it makes no sense to support the
> rule matching only on the payload but without matching type filed.
> 
> The DW samples should be stored after the flex parser creation for
> eCPRI. There is no need to query the sample IDs each time when
> creating a flow rule with eCPRI item. It will not introduce
> insertion rate degradation significantly.
> 
> Signed-off-by: Bing Zhao <bingz@mellanox.com>
> ---
>  drivers/common/mlx5/mlx5_prm.h  |  16 ++++-
>  drivers/net/mlx5/mlx5.h         |  15 +++++
>  drivers/net/mlx5/mlx5_flow_dv.c | 130 ++++++++++++++++++++++++++++++++++++++++
>  3 files changed, 160 insertions(+), 1 deletion(-)

In this patch, you could add the feature in the release notes,
as part of mlx5 section, and probably in the mlx5 guide too.
Bing Zhao July 9, 2020, 2:47 p.m. UTC | #2
Got it, I will add it.
Thanks for your comments.

BR. Bing

> -----Original Message-----
> From: Thomas Monjalon <thomas@monjalon.net>
> Sent: Thursday, July 9, 2020 8:22 PM
> To: Bing Zhao <bingz@mellanox.com>
> Cc: Ori Kam <orika@mellanox.com>; Slava Ovsiienko
> <viacheslavo@mellanox.com>; Raslan Darawsheh
> <rasland@mellanox.com>; Matan Azrad <matan@mellanox.com>;
> dev@dpdk.org
> Subject: Re: [dpdk-dev] [PATCH 2/5] net/mlx5: add flow translation of
> eCPRI header
> 
> 08/07/2020 16:43, Bing Zhao:
> > In the translation stage, the eCPRI item should be translated into the
> > format that lower layer driver could use. All the fields that need to
> > matched must be in network byte order after translation, as well as
> > the mask. Since the header in the item belongs to the network layers
> > stack, and the input parameter of the header is considered to be in
> > big-endian format already.
> >
> > Base on the definition in the PRM, the DW samples will be used for
> > matching in the FTE/STE. Now, the type field and only the PC ID, RTC
> > ID, and DLY MSR ID of the payload will be supported. The masks
> should
> > be 00 ff 00 00 ff ff(00) 00 00 in the network order. Two DWs are
> > needed to support such matching. The mask fields could be zeros to
> > support some wildcard rules. But it makes no sense to support the
> rule
> > matching only on the payload but without matching type filed.
> >
> > The DW samples should be stored after the flex parser creation for
> > eCPRI. There is no need to query the sample IDs each time when
> > creating a flow rule with eCPRI item. It will not introduce insertion
> > rate degradation significantly.
> >
> > Signed-off-by: Bing Zhao <bingz@mellanox.com>
> > ---
> >  drivers/common/mlx5/mlx5_prm.h  |  16 ++++-
> >  drivers/net/mlx5/mlx5.h         |  15 +++++
> >  drivers/net/mlx5/mlx5_flow_dv.c | 130
> > ++++++++++++++++++++++++++++++++++++++++
> >  3 files changed, 160 insertions(+), 1 deletion(-)
> 
> In this patch, you could add the feature in the release notes, as part of
> mlx5 section, and probably in the mlx5 guide too.
> 
> 
>

Patch
diff mbox series

diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h
index c63795f..decc63d 100644
--- a/drivers/common/mlx5/mlx5_prm.h
+++ b/drivers/common/mlx5/mlx5_prm.h
@@ -709,6 +709,18 @@  struct mlx5_ifc_fte_match_set_misc3_bits {
 	u8 reserved_at_170[0x90];
 };
 
+struct mlx5_ifc_fte_match_set_misc4_bits {
+	u8 prog_sample_field_value_0[0x20];
+	u8 prog_sample_field_id_0[0x20];
+	u8 prog_sample_field_value_1[0x20];
+	u8 prog_sample_field_id_1[0x20];
+	u8 prog_sample_field_value_2[0x20];
+	u8 prog_sample_field_id_2[0x20];
+	u8 prog_sample_field_value_3[0x20];
+	u8 prog_sample_field_id_3[0x20];
+	u8 reserved_at_100[0x100];
+};
+
 /* Flow matcher. */
 struct mlx5_ifc_fte_match_param_bits {
 	struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
@@ -716,6 +728,7 @@  struct mlx5_ifc_fte_match_param_bits {
 	struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
 	struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2;
 	struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3;
+	struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4;
 };
 
 enum {
@@ -723,7 +736,8 @@  enum {
 	MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT,
 	MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT,
 	MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT,
-	MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT
+	MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT,
+	MLX5_MATCH_CRITERIA_ENABLE_MISC4_BIT
 };
 
 enum {
diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h
index 46e66eb..51775ca 100644
--- a/drivers/net/mlx5/mlx5.h
+++ b/drivers/net/mlx5/mlx5.h
@@ -529,6 +529,19 @@  struct mlx5_flow_id_pool {
 	uint32_t max_id; /**< Maximum id can be allocated from the pool. */
 };
 
+/* Supported flex parser profile ID. */
+enum mlx5_flex_parser_profile_id {
+	MLX5_FLEX_PARSER_ECPRI_0 = 0,
+	MLX5_FLEX_PARSER_MAX = 8,
+};
+
+/* Sample ID information of flex parser structure. */
+struct mlx5_flex_parser_profiles {
+	uint32_t ids[4];	/* Sample IDs for this profile. */
+	void *obj;		/* Flex parser node object. */
+	uint32_t num;		/* Actual number of samples. */
+};
+
 /*
  * Shared Infiniband device context for Master/Representors
  * which belong to same IB device with multiple IB ports.
@@ -579,6 +592,8 @@  struct mlx5_dev_ctx_shared {
 	struct mlx5_devx_obj *tis; /* TIS object. */
 	struct mlx5_devx_obj *td; /* Transport domain. */
 	struct mlx5_flow_id_pool *flow_id_pool; /* Flow ID pool. */
+	struct mlx5_flex_parser_profiles fp[MLX5_FLEX_PARSER_MAX];
+	/* Flex parser profiles information. */
 	struct mlx5_dev_shared_port port[]; /* per device port data array. */
 };
 
diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c
index 6711c79..523d778 100644
--- a/drivers/net/mlx5/mlx5_flow_dv.c
+++ b/drivers/net/mlx5/mlx5_flow_dv.c
@@ -4779,6 +4779,34 @@  struct field_modify_info modify_tcp[] = {
 				  cnt, next);
 }
 
+static inline bool
+flow_dv_flex_parser_ecpri_exist(struct rte_eth_dev *dev)
+{
+	struct mlx5_priv *priv = dev->data->dev_private;
+	struct mlx5_flex_parser_profiles *prf =
+				&priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
+
+	return !!prf->obj;
+}
+
+
+static int
+flow_dv_flex_parser_ecpri_alloc(struct rte_eth_dev *dev)
+{
+	struct mlx5_priv *priv = dev->data->dev_private;
+	struct mlx5_flex_parser_profiles *prf =
+				&priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
+
+	return 0;
+}
+
+static void
+flow_dv_flex_parser_ecpri_release(struct rte_eth_dev *dev)
+{
+	(void)dev;
+	return;
+}
+
 /**
  * Verify the @p attributes will be correctly understood by the NIC and store
  * them in the @p flow if everything is correct.
@@ -7258,6 +7286,90 @@  struct field_modify_info modify_tcp[] = {
 		 rte_be_to_cpu_32(gtp_v->teid & gtp_m->teid));
 }
 
+/**
+ * Add eCPRI item to matcher and to the value.
+ *
+ * @param[in] dev
+ *   The devich to configure through.
+ * @param[in, out] matcher
+ *   Flow matcher.
+ * @param[in, out] key
+ *   Flow matcher value.
+ * @param[in] item
+ *   Flow pattern to translate.
+ * @param[in] samples
+ *   Sample IDs to be used in the matching.
+ */
+static void
+flow_dv_translate_item_ecpri(struct rte_eth_dev *dev, void *matcher,
+			     void *key, const struct rte_flow_item *item)
+{
+	struct mlx5_priv *priv = dev->data->dev_private;
+	const struct rte_flow_item_ecpri *ecpri_m = item->mask;
+	const struct rte_flow_item_ecpri *ecpri_v = item->spec;
+	void *misc4_m = MLX5_ADDR_OF(fte_match_param, matcher,
+				     misc_parameters_4);
+	void *misc4_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_4);
+	uint32_t *samples;
+	void *dw_m;
+	void *dw_v;
+
+	if (!ecpri_v)
+		return;
+	if (!ecpri_m)
+		ecpri_m = &rte_flow_item_ecpri_mask;
+	/*
+	 * Maximal four DW samples are supported in a single matching now.
+	 * Two are used now for a eCPRI matching:
+	 * 1. Type: one byte, mask should be 0x00ff0000 in network order
+	 * 2. ID of a message: one or two bytes, mask 0xffff0000 or 0xff000000
+	 *    if any.
+	 */
+	if (!ecpri_m->hdr.common.type)
+		return;
+	samples = priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0].ids;
+	/* Need to take the whole DW as the mask to fill the entry. */
+	dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
+			    prog_sample_field_value_0);
+	dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
+			    prog_sample_field_value_0);
+	/* Already big endian (network order) in the header. */
+	*(uint32_t *)dw_m = ecpri_m->hdr.dw0;
+	*(uint32_t *)dw_v = ecpri_v->hdr.dw0;
+	/* Sample#0, used for matching type, offset 0. */
+	MLX5_SET(fte_match_set_misc4, misc4_m,
+		 prog_sample_field_id_0, samples[0]);
+	/* It makes no sense to set the sample ID in the mask field. */
+	MLX5_SET(fte_match_set_misc4, misc4_v,
+		 prog_sample_field_id_0, samples[0]);
+	/*
+	 * Checking if message body part needs to be matched.
+	 * Some wildcard rules only matching type field should be supported.
+	 */
+	if (ecpri_m->hdr.dummy[0]) {
+		switch (ecpri_v->hdr.common.type) {
+		case RTE_ECPRI_MSG_TYPE_IQ_DATA:
+		case RTE_ECPRI_MSG_TYPE_RTC_CTRL:
+		case RTE_ECPRI_MSG_TYPE_DLY_MSR:
+			dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
+					    prog_sample_field_value_1);
+			dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
+					    prog_sample_field_value_1);
+			*(uint32_t *)dw_m = ecpri_m->hdr.dummy[0];
+			*(uint32_t *)dw_v = ecpri_v->hdr.dummy[0];
+			/* Sample#1, to match message body, offset 4. */
+			MLX5_SET(fte_match_set_misc4, misc4_m,
+				 prog_sample_field_id_1, samples[1]);
+			MLX5_SET(fte_match_set_misc4, misc4_v,
+				 prog_sample_field_id_1, samples[1]);
+			break;
+		default:
+			/* Others, do not match any sample ID. */
+			break;
+		}
+	}
+}
+
 static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };
 
 #define HEADER_IS_ZERO(match_criteria, headers)				     \
@@ -7293,6 +7405,9 @@  struct field_modify_info modify_tcp[] = {
 	match_criteria_enable |=
 		(!HEADER_IS_ZERO(match_criteria, misc_parameters_3)) <<
 		MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT;
+	match_criteria_enable |=
+		(!HEADER_IS_ZERO(match_criteria, misc_parameters_4)) <<
+		MLX5_MATCH_CRITERIA_ENABLE_MISC4_BIT;
 	return match_criteria_enable;
 }
 
@@ -8572,6 +8687,21 @@  struct field_modify_info modify_tcp[] = {
 				    MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
 			last_item = MLX5_FLOW_LAYER_GTP;
 			break;
+		case RTE_FLOW_ITEM_TYPE_ECPRI:
+			if (!flow_dv_flex_parser_ecpri_exist(dev)) {
+				ret = flow_dv_flex_parser_ecpri_alloc(dev);
+				if (ret)
+					return rte_flow_error_set
+						(error, ret,
+						RTE_FLOW_ERROR_TYPE_ITEM,
+						NULL,
+						"cannot create eCPRI parser");
+			}
+			flow_dv_translate_item_ecpri(dev, match_mask,
+						     match_value, items);
+			/* No other protocol should follow eCPRI layer. */
+			last_item = MLX5_FLOW_LAYER_ECPRI;
+			break;
 		default:
 			break;
 		}