From patchwork Sun Jul 5 09:23:37 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ori Kam X-Patchwork-Id: 73121 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 9645BA00C5; Sun, 5 Jul 2020 11:26:02 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 910EC1DB4D; Sun, 5 Jul 2020 11:24:54 +0200 (CEST) Received: from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129]) by dpdk.org (Postfix) with ESMTP id E22491DB4D for ; Sun, 5 Jul 2020 11:24:52 +0200 (CEST) Received: from Internal Mail-Server by MTLPINE1 (envelope-from orika@mellanox.com) with SMTP; 5 Jul 2020 12:24:48 +0300 Received: from pegasus04.mtr.labs.mlnx. (pegasus04.mtr.labs.mlnx [10.210.16.126]) by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 0659OC3u028191; Sun, 5 Jul 2020 12:24:48 +0300 From: Ori Kam To: jerinj@marvell.com, xiang.w.wang@intel.com, matan@mellanox.com, viacheslavo@mellanox.com Cc: guyk@marvell.com, dev@dpdk.org, pbhagavatula@marvell.com, shahafs@mellanox.com, hemant.agrawal@nxp.com, opher@mellanox.com, alexr@mellanox.com, dovrat@marvell.com, pkapoor@marvell.com, nipun.gupta@nxp.com, bruce.richardson@intel.com, yang.a.hong@intel.com, harry.chang@intel.com, gu.jian1@zte.com.cn, shanjiangh@chinatelecom.cn, zhangy.yun@chinatelecom.cn, lixingfu@huachentel.com, wushuai@inspur.com, yuyingxia@yxlink.com, fanchenggang@sunyainfo.com, davidfgao@tencent.com, liuzhong1@chinaunicom.cn, zhaoyong11@huawei.com, oc@yunify.com, jim@netgate.com, hongjun.ni@intel.com, deri@ntop.org, fc@napatech.com, arthur.su@lionic.com, thomas@monjalon.net, orika@mellanox.com, rasland@mellanox.com Date: Sun, 5 Jul 2020 09:23:37 +0000 Message-Id: <1593941027-86651-11-git-send-email-orika@mellanox.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1593941027-86651-1-git-send-email-orika@mellanox.com> References: <1593941027-86651-1-git-send-email-orika@mellanox.com> Subject: [dpdk-dev] [PATCH 10/20] regex/mlx5: add engine status check X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This commit checks the engine status. Signed-off-by: Ori Kam --- drivers/regex/mlx5/mlx5_regex.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/drivers/regex/mlx5/mlx5_regex.c b/drivers/regex/mlx5/mlx5_regex.c index d264ecd..c469a10 100644 --- a/drivers/regex/mlx5/mlx5_regex.c +++ b/drivers/regex/mlx5/mlx5_regex.c @@ -17,6 +17,7 @@ #include "mlx5_regex.h" #include "mlx5_regex_utils.h" +#include "mlx5_rxp_csrs.h" int mlx5_regex_logtype; @@ -49,6 +50,28 @@ mlx5_glue->free_device_list(ibv_list); return ibv_match; } +static int +mlx5_regex_engines_status(struct ibv_context *ctx, int num_engines) +{ + uint32_t fpga_ident = 0; + int err; + int i; + + for (i = 0; i < num_engines; i++) { + err = mlx5_devx_regex_register_read(ctx, i, + MLX5_RXP_CSR_IDENTIFIER, + &fpga_ident); + fpga_ident = (fpga_ident & (0x0000FFFF)); + if (err || fpga_ident != MLX5_RXP_IDENTIFER) { + DRV_LOG(ERR, "Failed setup RXP %d err %d database " + "memory 0x%x", i, err, fpga_ident); + if (!err) + err = EINVAL; + return err; + } + } + return 0; +} static void mlx5_regex_get_name(char *name, struct rte_pci_device *pci_dev __rte_unused) @@ -109,6 +132,11 @@ rte_errno = ENOTSUP; goto error; } + if (mlx5_regex_engines_status(ctx, 2)) { + DRV_LOG(ERR, "RegEx engine error."); + rte_errno = ENOMEM; + goto error; + } priv = rte_zmalloc("mlx5 regex device private", sizeof(*priv), RTE_CACHE_LINE_SIZE); if (!priv) {