From patchwork Tue May 12 20:40:14 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pavan Nikhilesh Bhagavatula X-Patchwork-Id: 70132 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 8A0C3A034F; Tue, 12 May 2020 22:40:43 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 6DC581BFE6; Tue, 12 May 2020 22:40:43 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by dpdk.org (Postfix) with ESMTP id A04CB1BFBD for ; Tue, 12 May 2020 22:40:42 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 04CKGiKN021639; Tue, 12 May 2020 13:40:39 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0818; bh=6Crs+HPz+8jeCaZ49yjNaMjDF4PSUH2t1sKG45HHWkI=; b=bQRtKX83F2xuRefbO7ZzOBlDMhzcQ6fM/3jf63V7xU7yeP3QkoQP4oBVeBIaBW3JzagZ RnWACvuxCZqGvqVmwVrfGsnVgB5oi/UbqX5ONVqhpw95ivDcIHWPrbdQkWk99LbHwZBw stx/bcLjLC63nR9dnMVfYLDM0zNoSbv0L+HJ7MLFNW0CeVEZl8I1aP8CzRU4qDfeyveg 1k09xZpXYmgcLZHyYrZaJ7SpLFZHOQcW/nOVb3Atg58S/FNXW5nlg+Ggvgty6T01qP6n 8ia8Ugv/DKh9aBHo8oSaRL7iT1xkhV4vZpS0TOoWrCgDDSiTVDw/FCJVl19T5ulpZL/Y Zw== Received: from sc-exch04.marvell.com ([199.233.58.184]) by mx0a-0016f401.pphosted.com with ESMTP id 3100xa8mwb-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Tue, 12 May 2020 13:40:39 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by SC-EXCH04.marvell.com (10.93.176.84) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 12 May 2020 13:40:37 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 12 May 2020 13:40:38 -0700 Received: from BG-LT7430.marvell.com (BG-LT7430.marvell.com [10.28.161.240]) by maili.marvell.com (Postfix) with ESMTP id 9EE193F7043; Tue, 12 May 2020 13:40:34 -0700 (PDT) From: To: , , , Yipeng Wang , "Sameh Gobriel" , Bruce Richardson , Ruifeng Wang CC: , Pavan Nikhilesh Date: Wed, 13 May 2020 02:10:14 +0530 Message-ID: <20200512204015.1963-1-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200429180515.5704-1-pbhagavatula@marvell.com> References: <20200429180515.5704-1-pbhagavatula@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.216, 18.0.676 definitions=2020-05-12_07:2020-05-11, 2020-05-12 signatures=0 Subject: [dpdk-dev] [RFC v2] hash: unify crc32 API header for x86 and ARM X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Pavan Nikhilesh Merge crc32 hash calculation public API headers for x86 and ARM. Select the best available CRC32 algorithm when unsupported algorithm on a given CPU architecture is requested by an application. Previously, if an application directly includes `rte_crc_arm64.h` without including `rte_hash_crc.h` it will fail to compile. Although, `rte_crc_arm64.h` is no longer needed make it a dummy file for ABI purposes. Signed-off-by: Pavan Nikhilesh --- v2 Changes: - Don't remove `rte_crc_arm64.h` for ABI purposes. - Revert function pointer approach for performance reasons. - Select the best available algorithm based on the arch when user passes an unsupported crc32 algorithm. app/test/test_hash.c | 6 ++ lib/librte_hash/meson.build | 6 +- lib/librte_hash/rte_crc_arm64.h | 175 +------------------------------- lib/librte_hash/rte_hash_crc.h | 153 ++++++++++++++++++++-------- 4 files changed, 122 insertions(+), 218 deletions(-) -- 2.17.1 diff --git a/app/test/test_hash.c b/app/test/test_hash.c index afa3a1a3c..7bd457dac 100644 --- a/app/test/test_hash.c +++ b/app/test/test_hash.c @@ -195,7 +195,13 @@ test_crc32_hash_alg_equiv(void) } /* Resetting to best available algorithm */ +#if defined RTE_ARCH_X86 rte_hash_crc_set_alg(CRC32_SSE42_x64); +#elif defined RTE_ARCH_ARM64 + rte_hash_crc_set_alg(CRC32_ARM64); +#else + rte_hash_crc_set_alg(CRC32_SW); +#endif if (i == CRC32_ITERATIONS) return 0; diff --git a/lib/librte_hash/meson.build b/lib/librte_hash/meson.build index 6ab46ae9d..8a3cf2f64 100644 --- a/lib/librte_hash/meson.build +++ b/lib/librte_hash/meson.build @@ -1,12 +1,14 @@ # SPDX-License-Identifier: BSD-3-Clause # Copyright(c) 2017 Intel Corporation -headers = files('rte_crc_arm64.h', - 'rte_fbk_hash.h', +headers = files('rte_fbk_hash.h', 'rte_hash_crc.h', 'rte_hash.h', 'rte_jhash.h', 'rte_thash.h') +if dpdk_conf.has('RTE_ARCH_ARM64') + headers += files('rte_crc_arm64.h') +endif sources = files('rte_cuckoo_hash.c', 'rte_fbk_hash.c') deps += ['ring'] diff --git a/lib/librte_hash/rte_crc_arm64.h b/lib/librte_hash/rte_crc_arm64.h index b4628cfc0..adfcafc7d 100644 --- a/lib/librte_hash/rte_crc_arm64.h +++ b/lib/librte_hash/rte_crc_arm64.h @@ -5,179 +5,6 @@ #ifndef _RTE_CRC_ARM64_H_ #define _RTE_CRC_ARM64_H_ -/** - * @file - * - * RTE CRC arm64 Hash - */ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include -#include -#include - -static inline uint32_t -crc32c_arm64_u8(uint8_t data, uint32_t init_val) -{ - __asm__ volatile( - "crc32cb %w[crc], %w[crc], %w[value]" - : [crc] "+r" (init_val) - : [value] "r" (data)); - return init_val; -} - -static inline uint32_t -crc32c_arm64_u16(uint16_t data, uint32_t init_val) -{ - __asm__ volatile( - "crc32ch %w[crc], %w[crc], %w[value]" - : [crc] "+r" (init_val) - : [value] "r" (data)); - return init_val; -} - -static inline uint32_t -crc32c_arm64_u32(uint32_t data, uint32_t init_val) -{ - __asm__ volatile( - "crc32cw %w[crc], %w[crc], %w[value]" - : [crc] "+r" (init_val) - : [value] "r" (data)); - return init_val; -} - -static inline uint32_t -crc32c_arm64_u64(uint64_t data, uint32_t init_val) -{ - __asm__ volatile( - "crc32cx %w[crc], %w[crc], %x[value]" - : [crc] "+r" (init_val) - : [value] "r" (data)); - return init_val; -} - -/** - * Allow or disallow use of arm64 SIMD instrinsics for CRC32 hash - * calculation. - * - * @param alg - * An OR of following flags: - * - (CRC32_SW) Don't use arm64 crc intrinsics - * - (CRC32_ARM64) Use ARMv8 CRC intrinsic if available - * - */ -static inline void -rte_hash_crc_set_alg(uint8_t alg) -{ - switch (alg) { - case CRC32_ARM64: - if (!rte_cpu_get_flag_enabled(RTE_CPUFLAG_CRC32)) - alg = CRC32_SW; - /* fall-through */ - case CRC32_SW: - crc32_alg = alg; - /* fall-through */ - default: - break; - } -} - -/* Setting the best available algorithm */ -RTE_INIT(rte_hash_crc_init_alg) -{ - rte_hash_crc_set_alg(CRC32_ARM64); -} - -/** - * Use single crc32 instruction to perform a hash on a 1 byte value. - * Fall back to software crc32 implementation in case arm64 crc intrinsics is - * not supported - * - * @param data - * Data to perform hash on. - * @param init_val - * Value to initialise hash generator. - * @return - * 32bit calculated hash value. - */ -static inline uint32_t -rte_hash_crc_1byte(uint8_t data, uint32_t init_val) -{ - if (likely(crc32_alg & CRC32_ARM64)) - return crc32c_arm64_u8(data, init_val); - - return crc32c_1byte(data, init_val); -} - -/** - * Use single crc32 instruction to perform a hash on a 2 bytes value. - * Fall back to software crc32 implementation in case arm64 crc intrinsics is - * not supported - * - * @param data - * Data to perform hash on. - * @param init_val - * Value to initialise hash generator. - * @return - * 32bit calculated hash value. - */ -static inline uint32_t -rte_hash_crc_2byte(uint16_t data, uint32_t init_val) -{ - if (likely(crc32_alg & CRC32_ARM64)) - return crc32c_arm64_u16(data, init_val); - - return crc32c_2bytes(data, init_val); -} - -/** - * Use single crc32 instruction to perform a hash on a 4 byte value. - * Fall back to software crc32 implementation in case arm64 crc intrinsics is - * not supported - * - * @param data - * Data to perform hash on. - * @param init_val - * Value to initialise hash generator. - * @return - * 32bit calculated hash value. - */ -static inline uint32_t -rte_hash_crc_4byte(uint32_t data, uint32_t init_val) -{ - if (likely(crc32_alg & CRC32_ARM64)) - return crc32c_arm64_u32(data, init_val); - - return crc32c_1word(data, init_val); -} - -/** - * Use single crc32 instruction to perform a hash on a 8 byte value. - * Fall back to software crc32 implementation in case arm64 crc intrinsics is - * not supported - * - * @param data - * Data to perform hash on. - * @param init_val - * Value to initialise hash generator. - * @return - * 32bit calculated hash value. - */ -static inline uint32_t -rte_hash_crc_8byte(uint64_t data, uint32_t init_val) -{ - if (likely(crc32_alg == CRC32_ARM64)) - return crc32c_arm64_u64(data, init_val); - - return crc32c_2words(data, init_val); -} - -#ifdef __cplusplus -} -#endif +#include "rte_hash_crc.h" #endif /* _RTE_CRC_ARM64_H_ */ diff --git a/lib/librte_hash/rte_hash_crc.h b/lib/librte_hash/rte_hash_crc.h index cf28031b3..eaba70c12 100644 --- a/lib/librte_hash/rte_hash_crc.h +++ b/lib/librte_hash/rte_hash_crc.h @@ -16,10 +16,12 @@ extern "C" { #endif #include -#include -#include + #include #include +#include +#include +#include /* Lookup tables for software implementation of CRC32C */ static const uint32_t crc32c_tables[8][256] = {{ @@ -322,7 +324,7 @@ crc32c_2bytes(uint16_t data, uint32_t init_val) } static inline uint32_t -crc32c_1word(uint32_t data, uint32_t init_val) +crc32c_4bytes(uint32_t data, uint32_t init_val) { uint32_t crc, term1, term2; crc = init_val; @@ -336,7 +338,7 @@ crc32c_1word(uint32_t data, uint32_t init_val) } static inline uint32_t -crc32c_2words(uint64_t data, uint32_t init_val) +crc32c_8bytes(uint64_t data, uint32_t init_val) { uint32_t crc, term1, term2; union { @@ -358,6 +360,48 @@ crc32c_2words(uint64_t data, uint32_t init_val) return crc; } +#if defined(RTE_ARCH_ARM64) && defined(RTE_MACHINE_CPUFLAG_CRC32) +static inline uint32_t +crc32c_arm64_u8(uint8_t data, uint32_t init_val) +{ + __asm__ volatile( + "crc32cb %w[crc], %w[crc], %w[value]" + : [crc] "+r" (init_val) + : [value] "r" (data)); + return init_val; +} + +static inline uint32_t +crc32c_arm64_u16(uint16_t data, uint32_t init_val) +{ + __asm__ volatile( + "crc32ch %w[crc], %w[crc], %w[value]" + : [crc] "+r" (init_val) + : [value] "r" (data)); + return init_val; +} + +static inline uint32_t +crc32c_arm64_u32(uint32_t data, uint32_t init_val) +{ + __asm__ volatile( + "crc32cw %w[crc], %w[crc], %w[value]" + : [crc] "+r" (init_val) + : [value] "r" (data)); + return init_val; +} + +static inline uint32_t +crc32c_arm64_u64(uint64_t data, uint32_t init_val) +{ + __asm__ volatile( + "crc32cx %w[crc], %w[crc], %x[value]" + : [crc] "+r" (init_val) + : [value] "r" (data)); + return init_val; +} +#endif + #if defined(RTE_ARCH_X86) static inline uint32_t crc32c_sse42_u8(uint8_t data, uint32_t init_val) @@ -424,42 +468,69 @@ crc32c_sse42_u64(uint64_t data, uint64_t init_val) static uint8_t crc32_alg = CRC32_SW; -#if defined(RTE_ARCH_ARM64) && defined(RTE_MACHINE_CPUFLAG_CRC32) -#include "rte_crc_arm64.h" -#else - /** - * Allow or disallow use of SSE4.2 instrinsics for CRC32 hash + * Allow or disallow use of SSE4.2/ARMv8 instrinsics for CRC32 hash * calculation. * * @param alg * An OR of following flags: - * - (CRC32_SW) Don't use SSE4.2 intrinsics + * - (CRC32_SW) Don't use SSE4.2 intrinsics (default non-[x86/ARMv8]) * - (CRC32_SSE42) Use SSE4.2 intrinsics if available - * - (CRC32_SSE42_x64) Use 64-bit SSE4.2 intrinsic if available (default) - * + * - (CRC32_SSE42_x64) Use 64-bit SSE4.2 intrinsic if available (default x86) + * - (CRC32_ARM64) Use ARMv8 CRC intrinsic if available */ static inline void rte_hash_crc_set_alg(uint8_t alg) { -#if defined(RTE_ARCH_X86) - if (alg == CRC32_SSE42_x64 && - !rte_cpu_get_flag_enabled(RTE_CPUFLAG_EM64T)) - alg = CRC32_SSE42; + switch (alg) { + case CRC32_SSE42_x64: + case CRC32_SSE42: +#if defined RTE_ARCH_X86 + if (!rte_cpu_get_flag_enabled(RTE_CPUFLAG_EM64T)) + crc32_alg = CRC32_SSE42; + else + crc32_alg = alg; +#endif +#if defined RTE_ARCH_ARM64 + RTE_LOG(WARNING, HASH, + "Incorrect CRC32 algorithm requested setting best" + "available algorithm on the architecture\n"); + rte_hash_crc_set_alg(CRC32_ARM64); +#endif + break; + case CRC32_ARM64: +#if defined RTE_ARCH_ARM64 + if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_CRC32)) + crc32_alg = CRC32_ARM64; #endif - crc32_alg = alg; +#if defined RTE_ARCH_X86 + RTE_LOG(WARNING, HASH, + "Incorrect CRC32 algorithm requested setting best" + "available algorithm on the architecture\n"); + rte_hash_crc_set_alg(CRC32_SSE42_x64); +#endif + break; + case CRC32_SW: + default: + crc32_alg = CRC32_SW; + break; + } } /* Setting the best available algorithm */ RTE_INIT(rte_hash_crc_init_alg) { +#if defined RTE_ARCH_X86 rte_hash_crc_set_alg(CRC32_SSE42_x64); +#elif defined RTE_ARCH_ARM64 + rte_hash_crc_set_alg(CRC32_ARM64); +#else + rte_hash_crc_set_alg(CRC32_SW); +#endif } /** - * Use single crc32 instruction to perform a hash on a byte value. - * Fall back to software crc32 implementation in case SSE4.2 is - * not supported + * Calculate crc32 hash value of 1bytes. * * @param data * Data to perform hash on. @@ -474,15 +545,15 @@ rte_hash_crc_1byte(uint8_t data, uint32_t init_val) #if defined RTE_ARCH_X86 if (likely(crc32_alg & CRC32_SSE42)) return crc32c_sse42_u8(data, init_val); +#elif defined RTE_ARCH_ARM64 + if (likely(crc32_alg & CRC32_ARM64)) + return crc32c_arm64_u8(data, init_val); #endif - return crc32c_1byte(data, init_val); } /** - * Use single crc32 instruction to perform a hash on a 2 bytes value. - * Fall back to software crc32 implementation in case SSE4.2 is - * not supported + * Calculate crc32 hash value of 2bytes. * * @param data * Data to perform hash on. @@ -497,15 +568,15 @@ rte_hash_crc_2byte(uint16_t data, uint32_t init_val) #if defined RTE_ARCH_X86 if (likely(crc32_alg & CRC32_SSE42)) return crc32c_sse42_u16(data, init_val); +#elif defined RTE_ARCH_ARM64 + if (likely(crc32_alg & CRC32_ARM64)) + return crc32c_arm64_u16(data, init_val); #endif - return crc32c_2bytes(data, init_val); } /** - * Use single crc32 instruction to perform a hash on a 4 byte value. - * Fall back to software crc32 implementation in case SSE4.2 is - * not supported + * Calculate crc32 hash value of 4bytes. * * @param data * Data to perform hash on. @@ -520,15 +591,15 @@ rte_hash_crc_4byte(uint32_t data, uint32_t init_val) #if defined RTE_ARCH_X86 if (likely(crc32_alg & CRC32_SSE42)) return crc32c_sse42_u32(data, init_val); +#elif defined RTE_ARCH_ARM64 + if (likely(crc32_alg & CRC32_ARM64)) + return crc32c_arm64_u32(data, init_val); #endif - - return crc32c_1word(data, init_val); + return crc32c_4bytes(data, init_val); } /** - * Use single crc32 instruction to perform a hash on a 8 byte value. - * Fall back to software crc32 implementation in case SSE4.2 is - * not supported + * Calculate crc32 hash value of 8bytes. * * @param data * Data to perform hash on. @@ -540,21 +611,19 @@ rte_hash_crc_4byte(uint32_t data, uint32_t init_val) static inline uint32_t rte_hash_crc_8byte(uint64_t data, uint32_t init_val) { -#ifdef RTE_ARCH_X86_64 - if (likely(crc32_alg == CRC32_SSE42_x64)) +#if defined RTE_ARCH_X86_64 + if (likely(crc32_alg & CRC32_SSE42_x64)) return crc32c_sse42_u64(data, init_val); -#endif - -#if defined RTE_ARCH_X86 +#elif defined RTE_ARCH_X86 if (likely(crc32_alg & CRC32_SSE42)) return crc32c_sse42_u64_mimic(data, init_val); +#elif defined RTE_ARCH_ARM64 + if (likely(crc32_alg & CRC32_ARM64)) + return crc32c_arm64_u64(data, init_val); #endif - - return crc32c_2words(data, init_val); + return crc32c_8bytes(data, init_val); } -#endif - /** * Calculate CRC32 hash on user-supplied byte array. *