From patchwork Fri Apr 10 16:41:27 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gavin Hu X-Patchwork-Id: 68166 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id DE960A0598; Fri, 10 Apr 2020 18:42:50 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id ED4731D607; Fri, 10 Apr 2020 18:42:16 +0200 (CEST) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by dpdk.org (Postfix) with ESMTP id 6A2531D606 for ; Fri, 10 Apr 2020 18:42:15 +0200 (CEST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id F0B4630E; Fri, 10 Apr 2020 09:42:14 -0700 (PDT) Received: from net-arm-thunderx2-01.shanghai.arm.com (net-arm-thunderx2-01.shanghai.arm.com [10.169.41.214]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id C0FEB3F52E; Fri, 10 Apr 2020 09:42:10 -0700 (PDT) From: Gavin Hu To: dev@dpdk.org Cc: nd@arm.com, david.marchand@redhat.com, thomas@monjalon.net, rasland@mellanox.com, drc@linux.vnet.ibm.com, bruce.richardson@intel.com, konstantin.ananyev@intel.com, matan@mellanox.com, shahafs@mellanox.com, viacheslavo@mellanox.com, jerinj@marvell.com, Honnappa.Nagarahalli@arm.com, ruifeng.wang@arm.com, phil.yang@arm.com, joyce.kong@arm.com, steve.capper@arm.com Date: Sat, 11 Apr 2020 00:41:27 +0800 Message-Id: <20200410164127.54229-8-gavin.hu@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200410164127.54229-1-gavin.hu@arm.com> References: <20200410164127.54229-1-gavin.hu@arm.com> In-Reply-To: <20200213123854.203566-1-gavin.hu@arm.com> References: <20200213123854.203566-1-gavin.hu@arm.com> Subject: [dpdk-dev] [PATCH RFC v2 7/7] doc: clarify one configuration in mlx5 guide X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" The 'tx_db_nc' is used to differntiate two mapping types, WC and non-WC, both are actually non-cacheable. The Write-Combining on x86, is not-cacheablei. The Normal-NC, the counterpart on aarch64, is non-cacheable too, as its name suggests, the cache hierarchy was bypassed for accesses to these two memory regions. Interpreting it to 'non-cacheable' makes no distinction and is confusing. re-interprete it to 'non-combining' can make the distinction. Also explains why aarch64 default setting for this is different. Signed-off-by: Gavin Hu --- doc/guides/nics/mlx5.rst | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst index afd11cd83..addec9f12 100644 --- a/doc/guides/nics/mlx5.rst +++ b/doc/guides/nics/mlx5.rst @@ -610,9 +610,9 @@ Run-time configuration The rdma core library can map doorbell register in two ways, depending on the environment variable "MLX5_SHUT_UP_BF": - - As regular cached memory (usually with write combining attribute), if the + - As regular memory (usually with write combining attribute), if the variable is either missing or set to zero. - - As non-cached memory, if the variable is present and set to not "0" value. + - As non-combining memory, if the variable is present and set to not "0" value. The type of mapping may slightly affect the Tx performance, the optimal choice is strongly relied on the host architecture and should be deduced practically. @@ -638,6 +638,8 @@ Run-time configuration If ``tx_db_nc`` is omitted or set to zero, the preset (if any) environment variable "MLX5_SHUT_UP_BF" value is used. If there is no "MLX5_SHUT_UP_BF", the default ``tx_db_nc`` value is zero for ARM64 hosts and one for others. + ARM64 is different because it has a gathering buffer, the enforced barrier + can evict the doorbell ring immediately. - ``tx_vec_en`` parameter [int]