From patchwork Fri Apr 10 16:41:24 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gavin Hu X-Patchwork-Id: 68163 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id A29FEA0598; Fri, 10 Apr 2020 18:42:23 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id E08391D5F0; Fri, 10 Apr 2020 18:42:02 +0200 (CEST) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by dpdk.org (Postfix) with ESMTP id 43D8C1D5EE; Fri, 10 Apr 2020 18:42:01 +0200 (CEST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C82CA30E; Fri, 10 Apr 2020 09:42:00 -0700 (PDT) Received: from net-arm-thunderx2-01.shanghai.arm.com (net-arm-thunderx2-01.shanghai.arm.com [10.169.41.214]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 59C3F3F52E; Fri, 10 Apr 2020 09:41:56 -0700 (PDT) From: Gavin Hu To: dev@dpdk.org Cc: nd@arm.com, david.marchand@redhat.com, thomas@monjalon.net, rasland@mellanox.com, drc@linux.vnet.ibm.com, bruce.richardson@intel.com, konstantin.ananyev@intel.com, matan@mellanox.com, shahafs@mellanox.com, viacheslavo@mellanox.com, jerinj@marvell.com, Honnappa.Nagarahalli@arm.com, ruifeng.wang@arm.com, phil.yang@arm.com, joyce.kong@arm.com, steve.capper@arm.com, stable@dpdk.org Date: Sat, 11 Apr 2020 00:41:24 +0800 Message-Id: <20200410164127.54229-5-gavin.hu@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200410164127.54229-1-gavin.hu@arm.com> References: <20200410164127.54229-1-gavin.hu@arm.com> In-Reply-To: <20200213123854.203566-1-gavin.hu@arm.com> References: <20200213123854.203566-1-gavin.hu@arm.com> Subject: [dpdk-dev] [PATCH RFC v2 4/7] net/mlx5: relax barrier for aarch64 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" To ensure the WQE and doorbell record, which reside in the host memory, are visible to HW before the blue frame, an ordered mlx5_uar_write call is sufficient, a rte_wmb is overkill for aarch64. Fixes: 6cb559d67b83 ("net/mlx5: add vectorized Rx/Tx burst for x86") Cc: stable@dpdk.org Signed-off-by: Gavin Hu Reviewed-by: Phil Yang --- drivers/net/mlx5/mlx5_rxtx.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/net/mlx5/mlx5_rxtx.h b/drivers/net/mlx5/mlx5_rxtx.h index da5d81350..228e37de5 100644 --- a/drivers/net/mlx5/mlx5_rxtx.h +++ b/drivers/net/mlx5/mlx5_rxtx.h @@ -658,8 +658,7 @@ mlx5_tx_dbrec_cond_wmb(struct mlx5_txq_data *txq, volatile struct mlx5_wqe *wqe, rte_cio_wmb(); *txq->qp_db = rte_cpu_to_be_32(txq->wqe_ci); /* Ensure ordering between DB record and BF copy. */ - rte_wmb(); - mlx5_uar_write64_relaxed(*src, dst, txq->uar_lock); + mlx5_uar_write64(*src, dst, txq->uar_lock); if (cond) rte_dma_wmb(); }