diff mbox series

[v3,12/30] net/ena/base: add error logs when preparing Tx

Message ID	20200408082921.31000-13-mk@semihalf.com (mailing list archive)
State	Accepted, archived
Delegated to:	Ferruh Yigit
Headers	From: Michal Krawczyk <mk@semihalf.com> To: dev@dpdk.org Cc: mw@semihalf.com, mba@semihalf.com, gtzalik@amazon.com, evgenys@amazon.com, igorch@amazon.com, ferruh.yigit@intel.com, arybchenko@solarflare.com, Michal Krawczyk <mk@semihalf.com> Date: Wed, 8 Apr 2020 10:29:03 +0200 Message-Id: <20200408082921.31000-13-mk@semihalf.com> In-Reply-To: <20200408082921.31000-1-mk@semihalf.com> References: <20200408082921.31000-1-mk@semihalf.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Subject: [dpdk-dev] [PATCH v3 12/30] net/ena/base: add error logs when preparing Tx Precedence: list Errors-To: dev-bounces@dpdk.org Sender: "dev" <dev-bounces@dpdk.org>
Series	Update ENA driver to v2.1.0 \| [v3,00/30] Update ENA driver to v2.1.0 [v3,01/30] net/ena: check if size of buffer is at least 1400B [v3,02/30] net/ena/base: make allocation macros thread-safe [v3,03/30] net/ena/base: prevent allocation of 0-sized memory [v3,04/30] net/ena/base: generate default, random RSS hash key [v3,05/30] net/ena/base: fix testing for supported hash func [v3,06/30] net/ena/base: remove conversion of the ind tbl [v3,07/30] net/ena/base: rework interrupt moderation [v3,08/30] net/ena/base: remove extra properties strings [v3,09/30] net/ena/base: add accelerated LLQ mode [v3,10/30] net/ena/base: fix documentation of the functions [v3,11/30] net/ena/base: fix indentation in cq polling [v3,12/30] net/ena/base: add error logs when preparing Tx [v3,13/30] net/ena/base: use 48-bit memory addresses in ena_com [v3,14/30] net/ena/base: fix types for printing timestamps [v3,15/30] net/ena/base: fix indentation of multiple defines [v3,16/30] net/ena/base: update gen date and commit [v3,17/30] net/ena: set IO ring size to the valid value [v3,18/30] net/ena: refactor getting IO queues capabilities [v3,19/30] net/ena: add support for large LLQ headers [v3,20/30] net/ena: remove memory barriers before doorbells [v3,21/30] net/ena: add Tx drops statistic [v3,22/30] net/ena: disable meta caching [v3,23/30] net/ena: refactor Rx path [v3,24/30] net/ena: rework getting number of available descs [v3,25/30] net/ena: limit refill threshold by fixed value [v3,26/30] net/ena: use macros for ring idx operations [v3,27/30] net/ena: refactor Tx path [v3,28/30] net/ena: reuse 0 length Rx descriptor [v3,29/30] doc: add notes on ENA usage on metal instances [v3,30/30] net/ena: update version of the driver to v2.1.0

Checks

Context	Check	Description
ci/checkpatch	warning	coding style issues
ci/Intel-compilation	success	Compilation OK

Commit Message

Michal Krawczyk April 8, 2020, 8:29 a.m. UTC

  To make the debugging easier, the error logs were added in the Tx path.

Signed-off-by: Michal Krawczyk <mk@semihalf.com>
Reviewed-by: Igor Chauskin <igorch@amazon.com>
Reviewed-by: Guy Tzalik <gtzalik@amazon.com>
---
 drivers/net/ena/base/ena_eth_com.c | 24 +++++++++++++++++++-----
 1 file changed, 19 insertions(+), 5 deletions(-)

diff mbox series

Patch

diff --git a/drivers/net/ena/base/ena_eth_com.c b/drivers/net/ena/base/ena_eth_com.c
index 8f9528bdff..80d35556cb 100644
--- a/drivers/net/ena/base/ena_eth_com.c
+++ b/drivers/net/ena/base/ena_eth_com.c
@@ -148,8 +148,10 @@  static int ena_com_close_bounce_buffer(struct ena_com_io_sq *io_sq)
 	if (pkt_ctrl->idx) {
 		rc = ena_com_write_bounce_buffer_to_dev(io_sq,
 							pkt_ctrl->curr_bounce_buf);
-		if (unlikely(rc))
+		if (unlikely(rc)) {
+			ena_trc_err("failed to write bounce buffer to device\n");
 			return rc;
+		}
 
 		pkt_ctrl->curr_bounce_buf =
 			ena_com_get_next_bounce_buffer(&io_sq->bounce_buf_ctrl);
@@ -179,8 +181,10 @@  static int ena_com_sq_update_llq_tail(struct ena_com_io_sq *io_sq)
 	if (!pkt_ctrl->descs_left_in_line) {
 		rc = ena_com_write_bounce_buffer_to_dev(io_sq,
 							pkt_ctrl->curr_bounce_buf);
-		if (unlikely(rc))
+		if (unlikely(rc)) {
+			ena_trc_err("failed to write bounce buffer to device\n");
 			return rc;
+		}
 
 		pkt_ctrl->curr_bounce_buf =
 			ena_com_get_next_bounce_buffer(&io_sq->bounce_buf_ctrl);
@@ -394,8 +398,10 @@  int ena_com_prepare_tx(struct ena_com_io_sq *io_sq,
 	}
 
 	if (unlikely(io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV
-		     && !buffer_to_push))
+		     && !buffer_to_push)) {
+		ena_trc_err("push header wasn't provided on LLQ mode\n");
 		return ENA_COM_INVAL;
+	}
 
 	rc = ena_com_write_header_to_bounce(io_sq, buffer_to_push, header_len);
 	if (unlikely(rc))
@@ -410,6 +416,8 @@  int ena_com_prepare_tx(struct ena_com_io_sq *io_sq,
 	/* If the caller doesn't want to send packets */
 	if (unlikely(!num_bufs && !header_len)) {
 		rc = ena_com_close_bounce_buffer(io_sq);
+		if (rc)
+			ena_trc_err("failed to write buffers to LLQ\n");
 		*nb_hw_desc = io_sq->tail - start_tail;
 		return rc;
 	}
@@ -469,8 +477,10 @@  int ena_com_prepare_tx(struct ena_com_io_sq *io_sq,
 		/* The first desc share the same desc as the header */
 		if (likely(i != 0)) {
 			rc = ena_com_sq_update_tail(io_sq);
-			if (unlikely(rc))
+			if (unlikely(rc)) {
+				ena_trc_err("failed to update sq tail\n");
 				return rc;
+			}
 
 			desc = get_sq_desc(io_sq);
 			if (unlikely(!desc))
@@ -499,10 +509,14 @@  int ena_com_prepare_tx(struct ena_com_io_sq *io_sq,
 	desc->len_ctrl |= ENA_ETH_IO_TX_DESC_LAST_MASK;
 
 	rc = ena_com_sq_update_tail(io_sq);
-	if (unlikely(rc))
+	if (unlikely(rc)) {
+		ena_trc_err("failed to update sq tail of the last descriptor\n");
 		return rc;
+	}
 
 	rc = ena_com_close_bounce_buffer(io_sq);
+	if (rc)
+		ena_trc_err("failed when closing bounce buffer\n");
 
 	*nb_hw_desc = io_sq->tail - start_tail;
 	return rc;