From patchwork Mon Mar 30 00:02:51 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Chautru, Nicolas" X-Patchwork-Id: 67372 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 0894BA0562; Mon, 30 Mar 2020 02:04:34 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 18E941C036; Mon, 30 Mar 2020 02:04:01 +0200 (CEST) Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by dpdk.org (Postfix) with ESMTP id 0B9972BAE for ; Mon, 30 Mar 2020 02:03:52 +0200 (CEST) IronPort-SDR: TNYWuIhIjdF84EzZ6gr2W+kbgPsw+5dS+yJ4GpW5j1hrw+j/mdndWZXsvtDHxiKtMlQidoQuMa J9rSJwxbOZCA== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Mar 2020 17:03:51 -0700 IronPort-SDR: +haHCHPjiMw6Vi3D4P7DpurYdH56AQSHUR+am4Z9bLPJmqj5nAZR6wXauuhCwm3C9Q6GVcvHNq uKaNXaU8D0TQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.72,322,1580803200"; d="scan'208";a="248455339" Received: from skx-5gnr-sc12-4.sc.intel.com ([172.25.69.210]) by orsmga003.jf.intel.com with ESMTP; 29 Mar 2020 17:03:50 -0700 From: Nicolas Chautru To: dev@dpdk.org, akhil.goyal@nxp.com Cc: bruce.richardson@intel.com, Nicolas Chautru Date: Sun, 29 Mar 2020 17:02:51 -0700 Message-Id: <1585526580-113508-5-git-send-email-nicolas.chautru@intel.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1585526580-113508-1-git-send-email-nicolas.chautru@intel.com> References: <1585526580-113508-1-git-send-email-nicolas.chautru@intel.com> Subject: [dpdk-dev] [PATCH v2 04/13] baseband/fpga_5gnr_fec: add register definition file X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add in the list of registers for the device and related HW specs definitions. Signed-off-by: Nicolas Chautru --- drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.h | 189 +++++++++++++++++++++ 1 file changed, 189 insertions(+) diff --git a/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.h b/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.h index aeb1e94..b1416f6 100644 --- a/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.h +++ b/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.h @@ -30,6 +30,195 @@ #define FPGA_5GNR_FEC_PF_DEVICE_ID (0x0D8F) #define FPGA_5GNR_FEC_VF_DEVICE_ID (0x0D90) +/* Align DMA descriptors to 256 bytes - cache-aligned */ +#define FPGA_RING_DESC_ENTRY_LENGTH (8) +/* Ring size is in 256 bits (32 bytes) units */ +#define FPGA_RING_DESC_LEN_UNIT_BYTES (32) +/* Maximum size of queue */ +#define FPGA_RING_MAX_SIZE (1024) +#define FPGA_FLR_TIMEOUT_UNIT (16.384) + +#define FPGA_NUM_UL_QUEUES (32) +#define FPGA_NUM_DL_QUEUES (32) +#define FPGA_TOTAL_NUM_QUEUES (FPGA_NUM_UL_QUEUES + FPGA_NUM_DL_QUEUES) +#define FPGA_NUM_INTR_VEC (FPGA_TOTAL_NUM_QUEUES - RTE_INTR_VEC_RXTX_OFFSET) + +#define FPGA_INVALID_HW_QUEUE_ID (0xFFFFFFFF) + +#define FPGA_QUEUE_FLUSH_TIMEOUT_US (1000) +#define FPGA_HARQ_RDY_TIMEOUT (10) +#define FPGA_TIMEOUT_CHECK_INTERVAL (5) +#define FPGA_DDR_OVERFLOW (0x10) + +#define FPGA_5GNR_FEC_DDR_WR_DATA_LEN_IN_BYTES 8 +#define FPGA_5GNR_FEC_DDR_RD_DATA_LEN_IN_BYTES 8 + + +/* FPGA 5GNR FEC Register mapping on BAR0 */ +enum { + FPGA_5GNR_FEC_VERSION_ID = 0x00000000, /* len: 4B */ + FPGA_5GNR_FEC_CONFIGURATION = 0x00000004, /* len: 2B */ + FPGA_5GNR_FEC_QUEUE_PF_VF_MAP_DONE = 0x00000008, /* len: 1B */ + FPGA_5GNR_FEC_LOAD_BALANCE_FACTOR = 0x0000000a, /* len: 2B */ + FPGA_5GNR_FEC_RING_DESC_LEN = 0x0000000c, /* len: 2B */ + FPGA_5GNR_FEC_FLR_TIME_OUT = 0x0000000e, /* len: 2B */ + FPGA_5GNR_FEC_VFQ_FLUSH_STATUS_LW = 0x00000018, /* len: 4B */ + FPGA_5GNR_FEC_VFQ_FLUSH_STATUS_HI = 0x0000001c, /* len: 4B */ + FPGA_5GNR_FEC_QUEUE_MAP = 0x00000040, /* len: 256B */ + FPGA_5GNR_FEC_RING_CTRL_REGS = 0x00000200, /* len: 2048B */ + FPGA_5GNR_FEC_DDR4_WR_ADDR_REGS = 0x00000A00, /* len: 4B */ + FPGA_5GNR_FEC_DDR4_WR_DATA_REGS = 0x00000A08, /* len: 8B */ + FPGA_5GNR_FEC_DDR4_WR_DONE_REGS = 0x00000A10, /* len: 1B */ + FPGA_5GNR_FEC_DDR4_RD_ADDR_REGS = 0x00000A18, /* len: 4B */ + FPGA_5GNR_FEC_DDR4_RD_DONE_REGS = 0x00000A20, /* len: 1B */ + FPGA_5GNR_FEC_DDR4_RD_RDY_REGS = 0x00000A28, /* len: 1B */ + FPGA_5GNR_FEC_DDR4_RD_DATA_REGS = 0x00000A30, /* len: 8B */ + FPGA_5GNR_FEC_DDR4_ADDR_RDY_REGS = 0x00000A38, /* len: 1B */ + FPGA_5GNR_FEC_HARQ_BUF_SIZE_RDY_REGS = 0x00000A40, /* len: 1B */ + FPGA_5GNR_FEC_HARQ_BUF_SIZE_REGS = 0x00000A48 /* len: 4B */ +}; + +/* FPGA 5GNR FEC Ring Control Registers */ +enum { + FPGA_5GNR_FEC_RING_HEAD_ADDR = 0x00000008, + FPGA_5GNR_FEC_RING_SIZE = 0x00000010, + FPGA_5GNR_FEC_RING_MISC = 0x00000014, + FPGA_5GNR_FEC_RING_ENABLE = 0x00000015, + FPGA_5GNR_FEC_RING_FLUSH_QUEUE_EN = 0x00000016, + FPGA_5GNR_FEC_RING_SHADOW_TAIL = 0x00000018, + FPGA_5GNR_FEC_RING_HEAD_POINT = 0x0000001C +}; + +/* FPGA 5GNR FEC DESCRIPTOR ERROR */ +enum { + DESC_ERR_NO_ERR = 0x0, + DESC_ERR_K_P_OUT_OF_RANGE = 0x1, + DESC_ERR_Z_C_NOT_LEGAL = 0x2, + DESC_ERR_DESC_OFFSET_ERR = 0x3, + DESC_ERR_DESC_READ_FAIL = 0x8, + DESC_ERR_DESC_READ_TIMEOUT = 0x9, + DESC_ERR_DESC_READ_TLP_POISONED = 0xA, + DESC_ERR_CB_READ_FAIL = 0xC, + DESC_ERR_CB_READ_TIMEOUT = 0xD, + DESC_ERR_CB_READ_TLP_POISONED = 0xE, + DESC_ERR_HBSTORE_ERR = 0xF +}; + + +/* FPGA 5GNR FEC DMA Encoding Request Descriptor */ +struct __attribute__((__packed__)) fpga_dma_enc_desc { + uint32_t done:1, + rsrvd0:7, + error:4, + rsrvd1:4, + num_null:10, + rsrvd2:6; + uint32_t ncb:15, + rsrvd3:1, + k0:16; + uint32_t irq_en:1, + crc_en:1, + rsrvd4:1, + qm_idx:3, + bg_idx:1, + zc:9, + desc_idx:10, + rsrvd5:6; + uint16_t rm_e; + uint16_t k_; + uint32_t out_addr_lw; + uint32_t out_addr_hi; + uint32_t in_addr_lw; + uint32_t in_addr_hi; + + union { + struct { + /* Virtual addresses used to retrieve SW context info */ + void *op_addr; + /* Stores information about total number of Code Blocks + * in currently processed Transport Block + */ + uint64_t cbs_in_op; + }; + + uint8_t sw_ctxt[FPGA_RING_DESC_LEN_UNIT_BYTES * + (FPGA_RING_DESC_ENTRY_LENGTH - 1)]; + }; +}; + + +/* FPGA 5GNR DPC FEC DMA Decoding Request Descriptor */ +struct __attribute__((__packed__)) fpga_dma_dec_desc { + uint32_t done:1, + iter:5, + et_pass:1, + crcb_pass:1, + error:4, + qm_idx:3, + max_iter:5, + bg_idx:1, + rsrvd0:1, + harqin_en:1, + zc:9; + uint32_t hbstroe_offset:22, + num_null:10; + uint32_t irq_en:1, + ncb:15, + desc_idx:10, + drop_crc24b:1, + crc24b_ind:1, + rv:2, + et_dis:1, + rsrvd2:1; + uint32_t harq_input_length:16, + rm_e:16;/*the inbound data byte length*/ + uint32_t out_addr_lw; + uint32_t out_addr_hi; + uint32_t in_addr_lw; + uint32_t in_addr_hi; + + union { + struct { + /* Virtual addresses used to retrieve SW context info */ + void *op_addr; + /* Stores information about total number of Code Blocks + * in currently processed Transport Block + */ + uint8_t cbs_in_op; + }; + + uint32_t sw_ctxt[8 * (FPGA_RING_DESC_ENTRY_LENGTH - 1)]; + }; +}; + +/* FPGA 5GNR DMA Descriptor */ +union fpga_dma_desc { + struct fpga_dma_enc_desc enc_req; + struct fpga_dma_dec_desc dec_req; +}; + +/* FPGA 5GNR FEC Ring Control Register */ +struct __attribute__((__packed__)) fpga_ring_ctrl_reg { + uint64_t ring_base_addr; + uint64_t ring_head_addr; + uint16_t ring_size:11; + uint16_t rsrvd0; + union { /* Miscellaneous register */ + uint8_t misc; + uint8_t max_ul_dec:5, + max_ul_dec_en:1, + rsrvd1:2; + }; + uint8_t enable; + uint8_t flush_queue_en; + uint8_t rsrvd2; + uint16_t shadow_tail; + uint16_t rsrvd3; + uint16_t head_point; + uint16_t rsrvd4; + +}; + /* Private data structure for each FPGA FEC device */ struct fpga_5gnr_fec_device { /** Base address of MMIO registers (BAR0) */