[10/10] net/enetc: init SI transactions attribute reg
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Commit Message
From: Alex Marginean <alexandru.marginean@nxp.com>
This was left to its default value. With the patch transactions are:
- coherent,
- do not allocate in downstream cache (there is none on LS1028a),
- merge surrounding data for BD writes,
- overwrite surrounding data for frame data writes.
Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
---
drivers/net/enetc/base/enetc_hw.h | 2 ++
drivers/net/enetc/enetc_ethdev.c | 6 ++++++
2 files changed, 8 insertions(+)
@@ -22,6 +22,8 @@
#define ENETC_SIMR 0x0
#define ENETC_SIMR_EN BIT(31)
+#define ENETC_SICAR0 0x40
+#define ENETC_SICAR0_COHERENT 0x2B2B6727
#define ENETC_SIPMAR0 0x80
#define ENETC_SIPMAR1 0x84
@@ -150,6 +150,12 @@ enetc_hardware_init(struct enetc_eth_hw *hw)
/* WA for Rx lock-up HW erratum */
enetc_port_wr(enetc_hw, ENETC_PM0_RX_FIFO, 1);
+ /* set ENETC transaction flags to coherent, don't allocate.
+ * BD writes merge with surrounding cache line data, frame data writes
+ * overwrite cache line.
+ */
+ enetc_wr(enetc_hw, ENETC_SICAR0, ENETC_SICAR0_COHERENT);
+
/* Enabling Station Interface */
enetc_wr(enetc_hw, ENETC_SIMR, ENETC_SIMR_EN);