[v2,1/2] crypto/nitrox: fix invalid CSR register address generation
diff mbox series

Message ID 20200225094642.29239-1-rnagadheeraj@marvell.com
State Superseded
Delegated to: akhil goyal
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Series
  • [v2,1/2] crypto/nitrox: fix invalid CSR register address generation
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Commit Message

Nagadheeraj Rottela Feb. 25, 2020, 9:46 a.m. UTC
If the NPS_PKT ring/port is greater than 8191 the NPS_PKT*() macros will
evaluate to incorrect values due to unintended sign extension from int
to unsigned long. To fix this, add UL suffix to the constants in these
macros.

Coverity issue: 349899, 349905, 349911, 349921, 349923

Fixes: 32e4930d5a3b ("crypto/nitrox: add hardware queue management")

Signed-off-by: Nagadheeraj Rottela <rnagadheeraj@marvell.com>
---
 drivers/crypto/nitrox/nitrox_csr.h | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

Comments

Akhil Goyal March 25, 2020, 9:10 a.m. UTC | #1
> 
> If the NPS_PKT ring/port is greater than 8191 the NPS_PKT*() macros will
> evaluate to incorrect values due to unintended sign extension from int
> to unsigned long. To fix this, add UL suffix to the constants in these
> macros.
> 
> Coverity issue: 349899, 349905, 349911, 349921, 349923
> 
> Fixes: 32e4930d5a3b ("crypto/nitrox: add hardware queue management")
> 
> Signed-off-by: Nagadheeraj Rottela <rnagadheeraj@marvell.com>
> ---
>  drivers/crypto/nitrox/nitrox_csr.h | 18 +++++++++---------
>  1 file changed, 9 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/crypto/nitrox/nitrox_csr.h
> b/drivers/crypto/nitrox/nitrox_csr.h
> index 8cd92e38b..b4c969b26 100644
> --- a/drivers/crypto/nitrox/nitrox_csr.h
> +++ b/drivers/crypto/nitrox/nitrox_csr.h
> @@ -12,15 +12,15 @@
>  #define NITROX_CSR_ADDR(bar_addr, offset) (bar_addr + (offset))
> 
>  /* NPS packet registers */
> -#define NPS_PKT_IN_INSTR_CTLX(_i)	(0x10060 + ((_i) * 0x40000))
> -#define NPS_PKT_IN_INSTR_BADDRX(_i)	(0x10068 + ((_i) * 0x40000))
> -#define NPS_PKT_IN_INSTR_RSIZEX(_i)	(0x10070 + ((_i) * 0x40000))
> -#define NPS_PKT_IN_DONE_CNTSX(_i)	(0x10080 + ((_i) * 0x40000))
> -#define NPS_PKT_IN_INSTR_BAOFF_DBELLX(_i)	(0x10078 + ((_i) * 0x40000))
> -#define NPS_PKT_IN_INT_LEVELSX(_i)		(0x10088 + ((_i) * 0x40000))
> -#define NPS_PKT_SLC_CTLX(_i)		(0x10000 + ((_i) * 0x40000))
> -#define NPS_PKT_SLC_CNTSX(_i)		(0x10008 + ((_i) * 0x40000))
> -#define NPS_PKT_SLC_INT_LEVELSX(_i)	(0x10010 + ((_i) * 0x40000))
> +#define NPS_PKT_IN_INSTR_CTLX(_i)	(0x10060UL + ((_i) * 0x40000UL))
> +#define NPS_PKT_IN_INSTR_BADDRX(_i)	(0x10068UL + ((_i) *
> 0x40000UL))
> +#define NPS_PKT_IN_INSTR_RSIZEX(_i)	(0x10070UL + ((_i) * 0x40000UL))
> +#define NPS_PKT_IN_DONE_CNTSX(_i)	(0x10080UL + ((_i) * 0x40000UL))
> +#define NPS_PKT_IN_INSTR_BAOFF_DBELLX(_i)	(0x10078UL + ((_i) *
> 0x40000UL))
> +#define NPS_PKT_IN_INT_LEVELSX(_i)		(0x10088UL + ((_i) *
> 0x40000UL))
> +#define NPS_PKT_SLC_CTLX(_i)		(0x10000UL + ((_i) * 0x40000UL))
> +#define NPS_PKT_SLC_CNTSX(_i)		(0x10008UL + ((_i) *
> 0x40000UL))
> +#define NPS_PKT_SLC_INT_LEVELSX(_i)	(0x10010UL + ((_i) * 0x40000UL))
> 
>  /* AQM Virtual Function Registers */
>  #define AQMQ_QSZX(_i)			(0x20008 + ((_i)*0x40000))

AQMQ_QSZX may also need to be updated.

Patch
diff mbox series

diff --git a/drivers/crypto/nitrox/nitrox_csr.h b/drivers/crypto/nitrox/nitrox_csr.h
index 8cd92e38b..b4c969b26 100644
--- a/drivers/crypto/nitrox/nitrox_csr.h
+++ b/drivers/crypto/nitrox/nitrox_csr.h
@@ -12,15 +12,15 @@ 
 #define NITROX_CSR_ADDR(bar_addr, offset) (bar_addr + (offset))
 
 /* NPS packet registers */
-#define NPS_PKT_IN_INSTR_CTLX(_i)	(0x10060 + ((_i) * 0x40000))
-#define NPS_PKT_IN_INSTR_BADDRX(_i)	(0x10068 + ((_i) * 0x40000))
-#define NPS_PKT_IN_INSTR_RSIZEX(_i)	(0x10070 + ((_i) * 0x40000))
-#define NPS_PKT_IN_DONE_CNTSX(_i)	(0x10080 + ((_i) * 0x40000))
-#define NPS_PKT_IN_INSTR_BAOFF_DBELLX(_i)	(0x10078 + ((_i) * 0x40000))
-#define NPS_PKT_IN_INT_LEVELSX(_i)		(0x10088 + ((_i) * 0x40000))
-#define NPS_PKT_SLC_CTLX(_i)		(0x10000 + ((_i) * 0x40000))
-#define NPS_PKT_SLC_CNTSX(_i)		(0x10008 + ((_i) * 0x40000))
-#define NPS_PKT_SLC_INT_LEVELSX(_i)	(0x10010 + ((_i) * 0x40000))
+#define NPS_PKT_IN_INSTR_CTLX(_i)	(0x10060UL + ((_i) * 0x40000UL))
+#define NPS_PKT_IN_INSTR_BADDRX(_i)	(0x10068UL + ((_i) * 0x40000UL))
+#define NPS_PKT_IN_INSTR_RSIZEX(_i)	(0x10070UL + ((_i) * 0x40000UL))
+#define NPS_PKT_IN_DONE_CNTSX(_i)	(0x10080UL + ((_i) * 0x40000UL))
+#define NPS_PKT_IN_INSTR_BAOFF_DBELLX(_i)	(0x10078UL + ((_i) * 0x40000UL))
+#define NPS_PKT_IN_INT_LEVELSX(_i)		(0x10088UL + ((_i) * 0x40000UL))
+#define NPS_PKT_SLC_CTLX(_i)		(0x10000UL + ((_i) * 0x40000UL))
+#define NPS_PKT_SLC_CNTSX(_i)		(0x10008UL + ((_i) * 0x40000UL))
+#define NPS_PKT_SLC_INT_LEVELSX(_i)	(0x10010UL + ((_i) * 0x40000UL))
 
 /* AQM Virtual Function Registers */
 #define AQMQ_QSZX(_i)			(0x20008 + ((_i)*0x40000))