net/octeontx2: enable full flow control for HIGIG
diff mbox series

Message ID 20200130160151.18000-1-kirankumark@marvell.com
State Superseded, archived
Headers show
Series
  • net/octeontx2: enable full flow control for HIGIG
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Context Check Description
ci/Intel-compilation fail apply issues
ci/travis-robot success Travis build: passed
ci/checkpatch success coding style OK

Commit Message

Kiran Kumar Kokkilagadda Jan. 30, 2020, 4:01 p.m. UTC
From: Kiran Kumar K <kirankumark@marvell.com>

Due to following errata (NIX-35687) 2019-03-20 A0 CatA Link
credit deadlock, We disabled Tx flow control. Add check to enable
the full flow control in HIGIG mode.

Signed-off-by: Kiran Kumar K <kirankumark@marvell.com>
---
 drivers/net/octeontx2/otx2_flow_ctrl.c | 1 +
 1 file changed, 1 insertion(+)

Patch
diff mbox series

diff --git a/drivers/net/octeontx2/otx2_flow_ctrl.c b/drivers/net/octeontx2/otx2_flow_ctrl.c
index c6d7b1971..1c6929e76 100644
--- a/drivers/net/octeontx2/otx2_flow_ctrl.c
+++ b/drivers/net/octeontx2/otx2_flow_ctrl.c
@@ -213,6 +213,7 @@  otx2_nix_update_flow_ctrl_mode(struct rte_eth_dev *eth_dev)
 
 	/* To avoid Link credit deadlock on Ax, disable Tx FC if it's enabled */
 	if (otx2_dev_is_Ax(dev) &&
+	    (dev->npc_flow.switch_header_type != OTX2_PRIV_FLAGS_HIGIG) &&
 	    (fc_conf.mode == RTE_FC_FULL || fc_conf.mode == RTE_FC_RX_PAUSE)) {
 		fc_conf.mode =
 				(fc_conf.mode == RTE_FC_FULL ||