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Thu, 30 Jan 2020 07:45:16 +0000 X-Mailer: git-send-email 2.17.1 X-Originating-IP: [165.204.157.251] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: 5f02e6e2-1e81-452f-6a1f-08d7a55859d7 X-MS-TrafficTypeDiagnostic: DM5PR1201MB2475: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:1122; X-Forefront-PRVS: 02981BE340 X-Forefront-Antispam-Report: SFV:NSPM; SFS:(10009020)(4636009)(39860400002)(376002)(366004)(346002)(396003)(136003)(199004)(189003)(36756003)(4326008)(6666004)(5660300002)(8676002)(81166006)(478600001)(26005)(450100002)(2906002)(186003)(16526019)(2616005)(81156014)(956004)(1076003)(8936002)(66946007)(6916009)(9686003)(6486002)(316002)(66556008)(66476007)(7696005)(52116002); DIR:OUT; SFP:1101; SCL:1; SRVR:DM5PR1201MB2475; H:DM5PR1201MB2474.namprd12.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; Received-SPF: None (protection.outlook.com: amd.com does not designate permitted sender hosts) X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: /+UuB74FSIl9nlTQ9Yap3hjzfN666D/dfkvtgc+gN3YLEYh7vXCgn9ltLG6GrCs4ttuPnJhSPGZy8yLVUYGdmnHIn4OeivHdg6+F5iNUxm9q8O0opC29qLmTOPws5Mx9sO3DYFCP+CM3HekpZN3WM3mX831GzApKzbdPxBJ6eC88rM98/2D06hQYVuMQ0Hvdd0Oa9ZVlMuKPOxh9CUbFcJpbw9OIVb9VRfiYWZ8I1Z/EzitunUbWyZop+kvHC3HnwjFyKgoSJDZSR3oTK9Nt9r1V17s1SnzGDGid/Jpjc+jvEnwBhT/7aeZfn5bC9G3xCY1DMnS/RyN1zNxSLnXVCc4r+t86NzKERrN9NTzP4ZZzY2A5kPC5uMGwrgw1bHWTf8XF4uuO8kYc6ZQ0EdgCYj8dKiOIM03O4w6ddxcH3C8PW/HGtl69+VghqZLhHM3l X-MS-Exchange-AntiSpam-MessageData: cV1VAHqyvOuL8pp2PdUUn3VI3rNUkgV2TbVDOnYV8EGYcxcWlLkEh/khOLWzn4+l0IzXH3ikHdXb2HdGLwE3RRQdvrbqZz3/ufmbFD9mDGp8dUcGJVuRDrCVVDkOqWs5Jl0+aImjyb9nzCkwCFhJaw== X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 5f02e6e2-1e81-452f-6a1f-08d7a55859d7 X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Jan 2020 07:45:18.5996 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: VLjpppQR4xogfHlttj/xSGZi7pUL2pZuCWL8a2z8tjc8n19FCzscjatRiGl4fjh+UDgkbjiEAyI0T4vAW4zVLQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR1201MB2475 Subject: [dpdk-dev] [PATCH v1] net/axgbe: support priority flow control API X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Amaranath Somalapuram adding api for priority_flow_ctrl_set adding dpdk priority flow control to set water high and low, pause_time and priority Signed-off-by: Amaranath Somalapuram --- drivers/net/axgbe/axgbe_common.h | 17 ++++++ drivers/net/axgbe/axgbe_dev.c | 1 + drivers/net/axgbe/axgbe_ethdev.c | 96 ++++++++++++++++++++++++++++++++ drivers/net/axgbe/axgbe_ethdev.h | 1 + 4 files changed, 115 insertions(+) diff --git a/drivers/net/axgbe/axgbe_common.h b/drivers/net/axgbe/axgbe_common.h index fdb037dd5..bc7bc6af5 100644 --- a/drivers/net/axgbe/axgbe_common.h +++ b/drivers/net/axgbe/axgbe_common.h @@ -833,6 +833,23 @@ #define MTL_TC_QWR_QW_INDEX 0 #define MTL_TC_QWR_QW_WIDTH 21 +#define MTL_TCPM0R_PSTC0_INDEX 0 +#define MTL_TCPM0R_PSTC0_WIDTH 8 +#define MTL_TCPM0R_PSTC1_INDEX 8 +#define MTL_TCPM0R_PSTC1_WIDTH 8 +#define MTL_TCPM0R_PSTC2_INDEX 16 +#define MTL_TCPM0R_PSTC2_WIDTH 8 +#define MTL_TCPM0R_PSTC3_INDEX 24 +#define MTL_TCPM0R_PSTC3_WIDTH 8 +#define MTL_TCPM1R_PSTC4_INDEX 0 +#define MTL_TCPM1R_PSTC4_WIDTH 8 +#define MTL_TCPM1R_PSTC5_INDEX 8 +#define MTL_TCPM1R_PSTC5_WIDTH 8 +#define MTL_TCPM1R_PSTC6_INDEX 16 +#define MTL_TCPM1R_PSTC6_WIDTH 8 +#define MTL_TCPM1R_PSTC7_INDEX 24 +#define MTL_TCPM1R_PSTC7_WIDTH 8 + /* MTL traffic class register value */ #define MTL_TSA_SP 0x00 #define MTL_TSA_ETS 0x02 diff --git a/drivers/net/axgbe/axgbe_dev.c b/drivers/net/axgbe/axgbe_dev.c index 83089f20d..9a68bea63 100644 --- a/drivers/net/axgbe/axgbe_dev.c +++ b/drivers/net/axgbe/axgbe_dev.c @@ -958,6 +958,7 @@ static void axgbe_config_queue_mapping(struct axgbe_port *pdata) if (i < qptc_extra) AXGMAC_MTL_IOWRITE_BITS(pdata, queue, MTL_Q_TQOMR, Q2TCMAP, i); + pdata->pfc_map[queue++] = i; } if (pdata->rss_enable) { diff --git a/drivers/net/axgbe/axgbe_ethdev.c b/drivers/net/axgbe/axgbe_ethdev.c index b88ad55ac..686a9a20d 100644 --- a/drivers/net/axgbe/axgbe_ethdev.c +++ b/drivers/net/axgbe/axgbe_ethdev.c @@ -48,6 +48,8 @@ static int axgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf); static int axgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf); +static int axgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, + struct rte_eth_pfc_conf *pfc_conf); struct axgbe_xstats { char name[RTE_ETH_XSTATS_NAME_SIZE]; @@ -176,6 +178,7 @@ static const struct eth_dev_ops axgbe_eth_dev_ops = { .tx_queue_release = axgbe_dev_tx_queue_release, .flow_ctrl_get = axgbe_flow_ctrl_get, .flow_ctrl_set = axgbe_flow_ctrl_set, + .priority_flow_ctrl_set = axgbe_priority_flow_ctrl_set, }; static int axgbe_phy_reset(struct axgbe_port *pdata) @@ -899,6 +902,99 @@ axgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) return 0; } +static int +axgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, + struct rte_eth_pfc_conf *pfc_conf) +{ + struct axgbe_port *pdata = dev->data->dev_private; + struct xgbe_fc_info fc = pdata->fc; + uint8_t tc_num; + + tc_num = pdata->pfc_map[pfc_conf->priority]; + + if (pfc_conf->priority >= pdata->hw_feat.tc_cnt) { + PMD_INIT_LOG(ERR, "Max supported traffic class: %d\n", + pdata->hw_feat.tc_cnt); + return -EINVAL; + } + + pdata->pause_autoneg = pfc_conf->fc.autoneg; + pdata->phy.pause_autoneg = pdata->pause_autoneg; + fc.send_xon = pfc_conf->fc.send_xon; + AXGMAC_MTL_IOWRITE_BITS(pdata, tc_num, MTL_Q_RQFCR, RFA, + AXGMAC_FLOW_CONTROL_VALUE(1024 * pfc_conf->fc.high_water)); + AXGMAC_MTL_IOWRITE_BITS(pdata, tc_num, MTL_Q_RQFCR, RFD, + AXGMAC_FLOW_CONTROL_VALUE(1024 * pfc_conf->fc.low_water)); + + switch (tc_num) { + case 0: + AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM0R, + PSTC0, pfc_conf->fc.pause_time); + break; + case 1: + AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM0R, + PSTC1, pfc_conf->fc.pause_time); + break; + case 2: + AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM0R, + PSTC2, pfc_conf->fc.pause_time); + break; + case 3: + AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM0R, + PSTC3, pfc_conf->fc.pause_time); + break; + case 4: + AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM1R, + PSTC4, pfc_conf->fc.pause_time); + break; + case 5: + AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM1R, + PSTC5, pfc_conf->fc.pause_time); + break; + case 7: + AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM1R, + PSTC6, pfc_conf->fc.pause_time); + break; + case 6: + AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM1R, + PSTC7, pfc_conf->fc.pause_time); + break; + } + + fc.mode = pfc_conf->fc.mode; + + if (fc.mode == RTE_FC_FULL) { + pdata->tx_pause = 1; + pdata->rx_pause = 1; + AXGMAC_IOWRITE_BITS(pdata, MAC_RFCR, PFCE, 1); + } else if (fc.mode == RTE_FC_RX_PAUSE) { + pdata->tx_pause = 0; + pdata->rx_pause = 1; + AXGMAC_IOWRITE_BITS(pdata, MAC_RFCR, PFCE, 1); + } else if (fc.mode == RTE_FC_TX_PAUSE) { + pdata->tx_pause = 1; + pdata->rx_pause = 0; + AXGMAC_IOWRITE_BITS(pdata, MAC_RFCR, PFCE, 0); + } else { + pdata->tx_pause = 0; + pdata->rx_pause = 0; + AXGMAC_IOWRITE_BITS(pdata, MAC_RFCR, PFCE, 0); + } + + if (pdata->tx_pause != (unsigned int)pdata->phy.tx_pause) + pdata->hw_if.config_tx_flow_control(pdata); + + if (pdata->rx_pause != (unsigned int)pdata->phy.rx_pause) + pdata->hw_if.config_rx_flow_control(pdata); + pdata->hw_if.config_flow_control(pdata); + pdata->phy.tx_pause = pdata->tx_pause; + pdata->phy.rx_pause = pdata->rx_pause; + + return 0; +} + + + static void axgbe_get_all_hw_features(struct axgbe_port *pdata) { unsigned int mac_hfr0, mac_hfr1, mac_hfr2; diff --git a/drivers/net/axgbe/axgbe_ethdev.h b/drivers/net/axgbe/axgbe_ethdev.h index 746fb2f15..c884f5642 100644 --- a/drivers/net/axgbe/axgbe_ethdev.h +++ b/drivers/net/axgbe/axgbe_ethdev.h @@ -585,6 +585,7 @@ struct axgbe_port { unsigned int rx_rfa[AXGBE_MAX_QUEUES]; unsigned int rx_rfd[AXGBE_MAX_QUEUES]; unsigned int fifo; + unsigned int pfc_map[AXGBE_MAX_QUEUES]; /* Receive Side Scaling settings */ u8 rss_key[AXGBE_RSS_HASH_KEY_SIZE];