[v1,01/38] net/mlx5: separate DevX commands interface
diff mbox series

Message ID 1579539790-3882-2-git-send-email-matan@mellanox.com
State Superseded, archived
Delegated to: Maxime Coquelin
Headers show
Series
  • Introduce mlx5 vDPA driver
Related show

Checks

Context Check Description
ci/Intel-compilation success Compilation OK
ci/checkpatch warning coding style issues

Commit Message

Matan Azrad Jan. 20, 2020, 5:02 p.m. UTC
The DevX commands interfaces is included in the mlx5.h file with a lot
of other PMD interfaces.

As an arrangement to make the DevX commands shared with different PMDs,
this patch moves the DevX interface to a new file called mlx5_devx_cmds.h.

Also remove shared device structure dependency from DevX commands.

Replace the DevX commands log mechanism from the mlx5 driver log
mechanism to the EAL log mechanism.

Signed-off-by: Matan Azrad <matan@mellanox.com>
---
 drivers/net/mlx5/mlx5.c           |   1 +
 drivers/net/mlx5/mlx5.h           | 219 +-----------------------------------
 drivers/net/mlx5/mlx5_devx_cmds.c |  33 +++---
 drivers/net/mlx5/mlx5_devx_cmds.h | 227 ++++++++++++++++++++++++++++++++++++++
 drivers/net/mlx5/mlx5_ethdev.c    |   1 +
 drivers/net/mlx5/mlx5_flow.c      |   5 +-
 drivers/net/mlx5/mlx5_flow_dv.c   |   1 +
 drivers/net/mlx5/mlx5_rxq.c       |   1 +
 drivers/net/mlx5/mlx5_rxtx.c      |   1 +
 drivers/net/mlx5/mlx5_txq.c       |   1 +
 drivers/net/mlx5/mlx5_vlan.c      |   1 +
 11 files changed, 259 insertions(+), 232 deletions(-)
 create mode 100644 drivers/net/mlx5/mlx5_devx_cmds.h

Patch
diff mbox series

diff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c
index ffee39c..2f91e50 100644
--- a/drivers/net/mlx5/mlx5.c
+++ b/drivers/net/mlx5/mlx5.c
@@ -46,6 +46,7 @@ 
 #include "mlx5_glue.h"
 #include "mlx5_mr.h"
 #include "mlx5_flow.h"
+#include "mlx5_devx_cmds.h"
 
 /* Device parameter to enable RX completion queue compression. */
 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h
index 01542e7..0b8b1b6 100644
--- a/drivers/net/mlx5/mlx5.h
+++ b/drivers/net/mlx5/mlx5.h
@@ -38,6 +38,7 @@ 
 #include "mlx5_defs.h"
 #include "mlx5_glue.h"
 #include "mlx5_prm.h"
+#include "mlx5_devx_cmds.h"
 
 enum {
 	PCI_VENDOR_ID_MELLANOX = 0x15b3,
@@ -156,60 +157,6 @@  struct mlx5_stats_ctrl {
 	uint64_t imissed_base;
 };
 
-/* devX creation object */
-struct mlx5_devx_obj {
-	struct mlx5dv_devx_obj *obj; /* The DV object. */
-	int id; /* The object ID. */
-};
-
-struct mlx5_devx_mkey_attr {
-	uint64_t addr;
-	uint64_t size;
-	uint32_t umem_id;
-	uint32_t pd;
-};
-
-/* HCA qos attributes. */
-struct mlx5_hca_qos_attr {
-	uint32_t sup:1;	/* Whether QOS is supported. */
-	uint32_t srtcm_sup:1; /* Whether srTCM mode is supported. */
-	uint8_t log_max_flow_meter;
-	/* Power of the maximum supported meters. */
-	uint8_t flow_meter_reg_c_ids;
-	/* Bitmap of the reg_Cs available for flow meter to use. */
-
-};
-
-/* HCA supports this number of time periods for LRO. */
-#define MLX5_LRO_NUM_SUPP_PERIODS 4
-
-/* HCA attributes. */
-struct mlx5_hca_attr {
-	uint32_t eswitch_manager:1;
-	uint32_t flow_counters_dump:1;
-	uint8_t flow_counter_bulk_alloc_bitmap;
-	uint32_t eth_net_offloads:1;
-	uint32_t eth_virt:1;
-	uint32_t wqe_vlan_insert:1;
-	uint32_t wqe_inline_mode:2;
-	uint32_t vport_inline_mode:3;
-	uint32_t tunnel_stateless_geneve_rx:1;
-	uint32_t geneve_max_opt_len:1; /* 0x0: 14DW, 0x1: 63DW */
-	uint32_t tunnel_stateless_gtp:1;
-	uint32_t lro_cap:1;
-	uint32_t tunnel_lro_gre:1;
-	uint32_t tunnel_lro_vxlan:1;
-	uint32_t lro_max_msg_sz_mode:2;
-	uint32_t lro_timer_supported_periods[MLX5_LRO_NUM_SUPP_PERIODS];
-	uint32_t flex_parser_protocols;
-	uint32_t hairpin:1;
-	uint32_t log_max_hairpin_queues:5;
-	uint32_t log_max_hairpin_wq_data_sz:5;
-	uint32_t log_max_hairpin_num_packets:5;
-	uint32_t vhca_id:16;
-	struct mlx5_hca_qos_attr qos;
-};
-
 /* Flow list . */
 TAILQ_HEAD(mlx5_flows, rte_flow);
 
@@ -289,133 +236,6 @@  struct mlx5_dev_config {
 	struct mlx5_lro_config lro; /* LRO configuration. */
 };
 
-struct mlx5_devx_wq_attr {
-	uint32_t wq_type:4;
-	uint32_t wq_signature:1;
-	uint32_t end_padding_mode:2;
-	uint32_t cd_slave:1;
-	uint32_t hds_skip_first_sge:1;
-	uint32_t log2_hds_buf_size:3;
-	uint32_t page_offset:5;
-	uint32_t lwm:16;
-	uint32_t pd:24;
-	uint32_t uar_page:24;
-	uint64_t dbr_addr;
-	uint32_t hw_counter;
-	uint32_t sw_counter;
-	uint32_t log_wq_stride:4;
-	uint32_t log_wq_pg_sz:5;
-	uint32_t log_wq_sz:5;
-	uint32_t dbr_umem_valid:1;
-	uint32_t wq_umem_valid:1;
-	uint32_t log_hairpin_num_packets:5;
-	uint32_t log_hairpin_data_sz:5;
-	uint32_t single_wqe_log_num_of_strides:4;
-	uint32_t two_byte_shift_en:1;
-	uint32_t single_stride_log_num_of_bytes:3;
-	uint32_t dbr_umem_id;
-	uint32_t wq_umem_id;
-	uint64_t wq_umem_offset;
-};
-
-/* Create RQ attributes structure, used by create RQ operation. */
-struct mlx5_devx_create_rq_attr {
-	uint32_t rlky:1;
-	uint32_t delay_drop_en:1;
-	uint32_t scatter_fcs:1;
-	uint32_t vsd:1;
-	uint32_t mem_rq_type:4;
-	uint32_t state:4;
-	uint32_t flush_in_error_en:1;
-	uint32_t hairpin:1;
-	uint32_t user_index:24;
-	uint32_t cqn:24;
-	uint32_t counter_set_id:8;
-	uint32_t rmpn:24;
-	struct mlx5_devx_wq_attr wq_attr;
-};
-
-/* Modify RQ attributes structure, used by modify RQ operation. */
-struct mlx5_devx_modify_rq_attr {
-	uint32_t rqn:24;
-	uint32_t rq_state:4; /* Current RQ state. */
-	uint32_t state:4; /* Required RQ state. */
-	uint32_t scatter_fcs:1;
-	uint32_t vsd:1;
-	uint32_t counter_set_id:8;
-	uint32_t hairpin_peer_sq:24;
-	uint32_t hairpin_peer_vhca:16;
-	uint64_t modify_bitmask;
-	uint32_t lwm:16; /* Contained WQ lwm. */
-};
-
-struct mlx5_rx_hash_field_select {
-	uint32_t l3_prot_type:1;
-	uint32_t l4_prot_type:1;
-	uint32_t selected_fields:30;
-};
-
-/* TIR attributes structure, used by TIR operations. */
-struct mlx5_devx_tir_attr {
-	uint32_t disp_type:4;
-	uint32_t lro_timeout_period_usecs:16;
-	uint32_t lro_enable_mask:4;
-	uint32_t lro_max_msg_sz:8;
-	uint32_t inline_rqn:24;
-	uint32_t rx_hash_symmetric:1;
-	uint32_t tunneled_offload_en:1;
-	uint32_t indirect_table:24;
-	uint32_t rx_hash_fn:4;
-	uint32_t self_lb_block:2;
-	uint32_t transport_domain:24;
-	uint32_t rx_hash_toeplitz_key[10];
-	struct mlx5_rx_hash_field_select rx_hash_field_selector_outer;
-	struct mlx5_rx_hash_field_select rx_hash_field_selector_inner;
-};
-
-/* RQT attributes structure, used by RQT operations. */
-struct mlx5_devx_rqt_attr {
-	uint32_t rqt_max_size:16;
-	uint32_t rqt_actual_size:16;
-	uint32_t rq_list[];
-};
-
-/* TIS attributes structure. */
-struct mlx5_devx_tis_attr {
-	uint32_t strict_lag_tx_port_affinity:1;
-	uint32_t tls_en:1;
-	uint32_t lag_tx_port_affinity:4;
-	uint32_t prio:4;
-	uint32_t transport_domain:24;
-};
-
-/* SQ attributes structure, used by SQ create operation. */
-struct mlx5_devx_create_sq_attr {
-	uint32_t rlky:1;
-	uint32_t cd_master:1;
-	uint32_t fre:1;
-	uint32_t flush_in_error_en:1;
-	uint32_t allow_multi_pkt_send_wqe:1;
-	uint32_t min_wqe_inline_mode:3;
-	uint32_t state:4;
-	uint32_t reg_umr:1;
-	uint32_t allow_swp:1;
-	uint32_t hairpin:1;
-	uint32_t user_index:24;
-	uint32_t cqn:24;
-	uint32_t packet_pacing_rate_limit_index:16;
-	uint32_t tis_lst_sz:16;
-	uint32_t tis_num:24;
-	struct mlx5_devx_wq_attr wq_attr;
-};
-
-/* SQ attributes structure, used by SQ modify operation. */
-struct mlx5_devx_modify_sq_attr {
-	uint32_t sq_state:4;
-	uint32_t state:4;
-	uint32_t hairpin_peer_rq:24;
-	uint32_t hairpin_peer_vhca:16;
-};
 
 /**
  * Type of object being allocated.
@@ -1022,43 +842,6 @@  void mlx5_vlan_vmwa_release(struct rte_eth_dev *dev,
 void mlx5_vlan_vmwa_acquire(struct rte_eth_dev *dev,
 			    struct mlx5_vf_vlan *vf_vlan);
 
-/* mlx5_devx_cmds.c */
-
-struct mlx5_devx_obj *mlx5_devx_cmd_flow_counter_alloc(struct ibv_context *ctx,
-						       uint32_t bulk_sz);
-int mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj);
-int mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs,
-				     int clear, uint32_t n_counters,
-				     uint64_t *pkts, uint64_t *bytes,
-				     uint32_t mkey, void *addr,
-				     struct mlx5dv_devx_cmd_comp *cmd_comp,
-				     uint64_t async_id);
-int mlx5_devx_cmd_query_hca_attr(struct ibv_context *ctx,
-				 struct mlx5_hca_attr *attr);
-struct mlx5_devx_obj *mlx5_devx_cmd_mkey_create(struct ibv_context *ctx,
-					     struct mlx5_devx_mkey_attr *attr);
-int mlx5_devx_get_out_command_status(void *out);
-int mlx5_devx_cmd_qp_query_tis_td(struct ibv_qp *qp, uint32_t tis_num,
-				  uint32_t *tis_td);
-struct mlx5_devx_obj *mlx5_devx_cmd_create_rq(struct ibv_context *ctx,
-				struct mlx5_devx_create_rq_attr *rq_attr,
-				int socket);
-int mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq,
-			    struct mlx5_devx_modify_rq_attr *rq_attr);
-struct mlx5_devx_obj *mlx5_devx_cmd_create_tir(struct ibv_context *ctx,
-					struct mlx5_devx_tir_attr *tir_attr);
-struct mlx5_devx_obj *mlx5_devx_cmd_create_rqt(struct ibv_context *ctx,
-					struct mlx5_devx_rqt_attr *rqt_attr);
-struct mlx5_devx_obj *mlx5_devx_cmd_create_sq
-	(struct ibv_context *ctx, struct mlx5_devx_create_sq_attr *sq_attr);
-int mlx5_devx_cmd_modify_sq
-	(struct mlx5_devx_obj *sq, struct mlx5_devx_modify_sq_attr *sq_attr);
-struct mlx5_devx_obj *mlx5_devx_cmd_create_tis
-	(struct ibv_context *ctx, struct mlx5_devx_tis_attr *tis_attr);
-struct mlx5_devx_obj *mlx5_devx_cmd_create_td(struct ibv_context *ctx);
-
-int mlx5_devx_cmd_flow_dump(struct mlx5_ibv_shared *sh, FILE *file);
-
 /* mlx5_flow_meter.c */
 
 int mlx5_flow_meter_ops_get(struct rte_eth_dev *dev, void *arg);
diff --git a/drivers/net/mlx5/mlx5_devx_cmds.c b/drivers/net/mlx5/mlx5_devx_cmds.c
index 9985d30..1302919 100644
--- a/drivers/net/mlx5/mlx5_devx_cmds.c
+++ b/drivers/net/mlx5/mlx5_devx_cmds.c
@@ -1,13 +1,15 @@ 
 // SPDX-License-Identifier: BSD-3-Clause
 /* Copyright 2018 Mellanox Technologies, Ltd */
 
+#include <unistd.h>
+
 #include <rte_flow_driver.h>
 #include <rte_malloc.h>
-#include <unistd.h>
 
-#include "mlx5.h"
-#include "mlx5_glue.h"
 #include "mlx5_prm.h"
+#include "mlx5_devx_cmds.h"
+#include "mlx5_utils.h"
+
 
 /**
  * Allocate flow counters via devx interface.
@@ -934,8 +936,12 @@  struct mlx5_devx_obj *
 /**
  * Dump all flows to file.
  *
- * @param[in] sh
- *   Pointer to context.
+ * @param[in] fdb_domain
+ *   FDB domain.
+ * @param[in] rx_domain
+ *   RX domain.
+ * @param[in] tx_domain
+ *   TX domain.
  * @param[out] file
  *   Pointer to file stream.
  *
@@ -943,23 +949,24 @@  struct mlx5_devx_obj *
  *   0 on success, a nagative value otherwise.
  */
 int
-mlx5_devx_cmd_flow_dump(struct mlx5_ibv_shared *sh __rte_unused,
-			FILE *file __rte_unused)
+mlx5_devx_cmd_flow_dump(void *fdb_domain __rte_unused,
+			void *rx_domain __rte_unused,
+			void *tx_domain __rte_unused, FILE *file __rte_unused)
 {
 	int ret = 0;
 
 #ifdef HAVE_MLX5_DR_FLOW_DUMP
-	if (sh->fdb_domain) {
-		ret = mlx5_glue->dr_dump_domain(file, sh->fdb_domain);
+	if (fdb_domain) {
+		ret = mlx5_glue->dr_dump_domain(file, fdb_domain);
 		if (ret)
 			return ret;
 	}
-	assert(sh->rx_domain);
-	ret = mlx5_glue->dr_dump_domain(file, sh->rx_domain);
+	assert(rx_domain);
+	ret = mlx5_glue->dr_dump_domain(file, rx_domain);
 	if (ret)
 		return ret;
-	assert(sh->tx_domain);
-	ret = mlx5_glue->dr_dump_domain(file, sh->tx_domain);
+	assert(tx_domain);
+	ret = mlx5_glue->dr_dump_domain(file, tx_domain);
 #else
 	ret = ENOTSUP;
 #endif
diff --git a/drivers/net/mlx5/mlx5_devx_cmds.h b/drivers/net/mlx5/mlx5_devx_cmds.h
new file mode 100644
index 0000000..0c5afde
--- /dev/null
+++ b/drivers/net/mlx5/mlx5_devx_cmds.h
@@ -0,0 +1,227 @@ 
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright 2019 Mellanox Technologies, Ltd
+ */
+
+#ifndef RTE_PMD_MLX5_DEVX_CMDS_H_
+#define RTE_PMD_MLX5_DEVX_CMDS_H_
+
+#include "mlx5_glue.h"
+
+/* devX creation object */
+struct mlx5_devx_obj {
+	struct mlx5dv_devx_obj *obj; /* The DV object. */
+	int id; /* The object ID. */
+};
+
+struct mlx5_devx_mkey_attr {
+	uint64_t addr;
+	uint64_t size;
+	uint32_t umem_id;
+	uint32_t pd;
+};
+
+/* HCA qos attributes. */
+struct mlx5_hca_qos_attr {
+	uint32_t sup:1;	/* Whether QOS is supported. */
+	uint32_t srtcm_sup:1; /* Whether srTCM mode is supported. */
+	uint8_t log_max_flow_meter;
+	/* Power of the maximum supported meters. */
+	uint8_t flow_meter_reg_c_ids;
+	/* Bitmap of the reg_Cs available for flow meter to use. */
+
+};
+
+/* HCA supports this number of time periods for LRO. */
+#define MLX5_LRO_NUM_SUPP_PERIODS 4
+
+struct mlx5_hca_attr {
+	uint32_t eswitch_manager:1;
+	uint32_t flow_counters_dump:1;
+	uint8_t flow_counter_bulk_alloc_bitmap;
+	uint32_t eth_net_offloads:1;
+	uint32_t eth_virt:1;
+	uint32_t wqe_vlan_insert:1;
+	uint32_t wqe_inline_mode:2;
+	uint32_t vport_inline_mode:3;
+	uint32_t tunnel_stateless_geneve_rx:1;
+	uint32_t geneve_max_opt_len:1; /* 0x0: 14DW, 0x1: 63DW */
+	uint32_t tunnel_stateless_gtp:1;
+	uint32_t lro_cap:1;
+	uint32_t tunnel_lro_gre:1;
+	uint32_t tunnel_lro_vxlan:1;
+	uint32_t lro_max_msg_sz_mode:2;
+	uint32_t lro_timer_supported_periods[MLX5_LRO_NUM_SUPP_PERIODS];
+	uint32_t flex_parser_protocols;
+	uint32_t hairpin:1;
+	uint32_t log_max_hairpin_queues:5;
+	uint32_t log_max_hairpin_wq_data_sz:5;
+	uint32_t log_max_hairpin_num_packets:5;
+	uint32_t vhca_id:16;
+	struct mlx5_hca_qos_attr qos;
+};
+
+struct mlx5_devx_wq_attr {
+	uint32_t wq_type:4;
+	uint32_t wq_signature:1;
+	uint32_t end_padding_mode:2;
+	uint32_t cd_slave:1;
+	uint32_t hds_skip_first_sge:1;
+	uint32_t log2_hds_buf_size:3;
+	uint32_t page_offset:5;
+	uint32_t lwm:16;
+	uint32_t pd:24;
+	uint32_t uar_page:24;
+	uint64_t dbr_addr;
+	uint32_t hw_counter;
+	uint32_t sw_counter;
+	uint32_t log_wq_stride:4;
+	uint32_t log_wq_pg_sz:5;
+	uint32_t log_wq_sz:5;
+	uint32_t dbr_umem_valid:1;
+	uint32_t wq_umem_valid:1;
+	uint32_t log_hairpin_num_packets:5;
+	uint32_t log_hairpin_data_sz:5;
+	uint32_t single_wqe_log_num_of_strides:4;
+	uint32_t two_byte_shift_en:1;
+	uint32_t single_stride_log_num_of_bytes:3;
+	uint32_t dbr_umem_id;
+	uint32_t wq_umem_id;
+	uint64_t wq_umem_offset;
+};
+
+/* Create RQ attributes structure, used by create RQ operation. */
+struct mlx5_devx_create_rq_attr {
+	uint32_t rlky:1;
+	uint32_t delay_drop_en:1;
+	uint32_t scatter_fcs:1;
+	uint32_t vsd:1;
+	uint32_t mem_rq_type:4;
+	uint32_t state:4;
+	uint32_t flush_in_error_en:1;
+	uint32_t hairpin:1;
+	uint32_t user_index:24;
+	uint32_t cqn:24;
+	uint32_t counter_set_id:8;
+	uint32_t rmpn:24;
+	struct mlx5_devx_wq_attr wq_attr;
+};
+
+/* Modify RQ attributes structure, used by modify RQ operation. */
+struct mlx5_devx_modify_rq_attr {
+	uint32_t rqn:24;
+	uint32_t rq_state:4; /* Current RQ state. */
+	uint32_t state:4; /* Required RQ state. */
+	uint32_t scatter_fcs:1;
+	uint32_t vsd:1;
+	uint32_t counter_set_id:8;
+	uint32_t hairpin_peer_sq:24;
+	uint32_t hairpin_peer_vhca:16;
+	uint64_t modify_bitmask;
+	uint32_t lwm:16; /* Contained WQ lwm. */
+};
+
+struct mlx5_rx_hash_field_select {
+	uint32_t l3_prot_type:1;
+	uint32_t l4_prot_type:1;
+	uint32_t selected_fields:30;
+};
+
+/* TIR attributes structure, used by TIR operations. */
+struct mlx5_devx_tir_attr {
+	uint32_t disp_type:4;
+	uint32_t lro_timeout_period_usecs:16;
+	uint32_t lro_enable_mask:4;
+	uint32_t lro_max_msg_sz:8;
+	uint32_t inline_rqn:24;
+	uint32_t rx_hash_symmetric:1;
+	uint32_t tunneled_offload_en:1;
+	uint32_t indirect_table:24;
+	uint32_t rx_hash_fn:4;
+	uint32_t self_lb_block:2;
+	uint32_t transport_domain:24;
+	uint32_t rx_hash_toeplitz_key[10];
+	struct mlx5_rx_hash_field_select rx_hash_field_selector_outer;
+	struct mlx5_rx_hash_field_select rx_hash_field_selector_inner;
+};
+
+/* RQT attributes structure, used by RQT operations. */
+struct mlx5_devx_rqt_attr {
+	uint32_t rqt_max_size:16;
+	uint32_t rqt_actual_size:16;
+	uint32_t rq_list[];
+};
+
+/* TIS attributes structure. */
+struct mlx5_devx_tis_attr {
+	uint32_t strict_lag_tx_port_affinity:1;
+	uint32_t tls_en:1;
+	uint32_t lag_tx_port_affinity:4;
+	uint32_t prio:4;
+	uint32_t transport_domain:24;
+};
+
+/* SQ attributes structure, used by SQ create operation. */
+struct mlx5_devx_create_sq_attr {
+	uint32_t rlky:1;
+	uint32_t cd_master:1;
+	uint32_t fre:1;
+	uint32_t flush_in_error_en:1;
+	uint32_t allow_multi_pkt_send_wqe:1;
+	uint32_t min_wqe_inline_mode:3;
+	uint32_t state:4;
+	uint32_t reg_umr:1;
+	uint32_t allow_swp:1;
+	uint32_t hairpin:1;
+	uint32_t user_index:24;
+	uint32_t cqn:24;
+	uint32_t packet_pacing_rate_limit_index:16;
+	uint32_t tis_lst_sz:16;
+	uint32_t tis_num:24;
+	struct mlx5_devx_wq_attr wq_attr;
+};
+
+/* SQ attributes structure, used by SQ modify operation. */
+struct mlx5_devx_modify_sq_attr {
+	uint32_t sq_state:4;
+	uint32_t state:4;
+	uint32_t hairpin_peer_rq:24;
+	uint32_t hairpin_peer_vhca:16;
+};
+
+/* mlx5_devx_cmds.c */
+
+struct mlx5_devx_obj *mlx5_devx_cmd_flow_counter_alloc(struct ibv_context *ctx,
+						       uint32_t bulk_sz);
+int mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj);
+int mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs,
+				     int clear, uint32_t n_counters,
+				     uint64_t *pkts, uint64_t *bytes,
+				     uint32_t mkey, void *addr,
+				     struct mlx5dv_devx_cmd_comp *cmd_comp,
+				     uint64_t async_id);
+int mlx5_devx_cmd_query_hca_attr(struct ibv_context *ctx,
+				 struct mlx5_hca_attr *attr);
+struct mlx5_devx_obj *mlx5_devx_cmd_mkey_create(struct ibv_context *ctx,
+					      struct mlx5_devx_mkey_attr *attr);
+int mlx5_devx_get_out_command_status(void *out);
+int mlx5_devx_cmd_qp_query_tis_td(struct ibv_qp *qp, uint32_t tis_num,
+				  uint32_t *tis_td);
+struct mlx5_devx_obj *mlx5_devx_cmd_create_rq(struct ibv_context *ctx,
+				       struct mlx5_devx_create_rq_attr *rq_attr,
+				       int socket);
+int mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq,
+			    struct mlx5_devx_modify_rq_attr *rq_attr);
+struct mlx5_devx_obj *mlx5_devx_cmd_create_tir(struct ibv_context *ctx,
+					   struct mlx5_devx_tir_attr *tir_attr);
+struct mlx5_devx_obj *mlx5_devx_cmd_create_rqt(struct ibv_context *ctx,
+					   struct mlx5_devx_rqt_attr *rqt_attr);
+struct mlx5_devx_obj *mlx5_devx_cmd_create_sq(struct ibv_context *ctx,
+				      struct mlx5_devx_create_sq_attr *sq_attr);
+int mlx5_devx_cmd_modify_sq(struct mlx5_devx_obj *sq,
+			    struct mlx5_devx_modify_sq_attr *sq_attr);
+struct mlx5_devx_obj *mlx5_devx_cmd_create_tis(struct ibv_context *ctx,
+					   struct mlx5_devx_tis_attr *tis_attr);
+struct mlx5_devx_obj *mlx5_devx_cmd_create_td(struct ibv_context *ctx);
+int mlx5_devx_cmd_flow_dump(void *fdb_domain, void *rx_domain, void *tx_domain,
+			    FILE *file);
+#endif /* RTE_PMD_MLX5_DEVX_CMDS_H_ */
diff --git a/drivers/net/mlx5/mlx5_ethdev.c b/drivers/net/mlx5/mlx5_ethdev.c
index 3b4c5db..ce0109c 100644
--- a/drivers/net/mlx5/mlx5_ethdev.c
+++ b/drivers/net/mlx5/mlx5_ethdev.c
@@ -38,6 +38,7 @@ 
 
 #include "mlx5.h"
 #include "mlx5_glue.h"
+#include "mlx5_devx_cmds.h"
 #include "mlx5_rxtx.h"
 #include "mlx5_utils.h"
 
diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c
index 970123b..34f3a53 100644
--- a/drivers/net/mlx5/mlx5_flow.c
+++ b/drivers/net/mlx5/mlx5_flow.c
@@ -31,6 +31,7 @@ 
 #include "mlx5_defs.h"
 #include "mlx5_flow.h"
 #include "mlx5_glue.h"
+#include "mlx5_devx_cmds.h"
 #include "mlx5_prm.h"
 #include "mlx5_rxtx.h"
 
@@ -5704,6 +5705,8 @@  struct mlx5_flow_counter *
 		   struct rte_flow_error *error __rte_unused)
 {
 	struct mlx5_priv *priv = dev->data->dev_private;
+	struct mlx5_ibv_shared *sh = priv->sh;
 
-	return mlx5_devx_cmd_flow_dump(priv->sh, file);
+	return mlx5_devx_cmd_flow_dump(sh->fdb_domain, sh->rx_domain,
+				       sh->tx_domain, file);
 }
diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c
index 5a1b426..d70dd4f 100644
--- a/drivers/net/mlx5/mlx5_flow_dv.c
+++ b/drivers/net/mlx5/mlx5_flow_dv.c
@@ -32,6 +32,7 @@ 
 #include "mlx5.h"
 #include "mlx5_defs.h"
 #include "mlx5_glue.h"
+#include "mlx5_devx_cmds.h"
 #include "mlx5_flow.h"
 #include "mlx5_prm.h"
 #include "mlx5_rxtx.h"
diff --git a/drivers/net/mlx5/mlx5_rxq.c b/drivers/net/mlx5/mlx5_rxq.c
index c936a7f..89168cd 100644
--- a/drivers/net/mlx5/mlx5_rxq.c
+++ b/drivers/net/mlx5/mlx5_rxq.c
@@ -37,6 +37,7 @@ 
 #include "mlx5_defs.h"
 #include "mlx5_glue.h"
 #include "mlx5_flow.h"
+#include "mlx5_devx_cmds.h"
 
 /* Default RSS hash key also used for ConnectX-3. */
 uint8_t rss_hash_default_key[] = {
diff --git a/drivers/net/mlx5/mlx5_rxtx.c b/drivers/net/mlx5/mlx5_rxtx.c
index 67cafd1..2eede1b 100644
--- a/drivers/net/mlx5/mlx5_rxtx.c
+++ b/drivers/net/mlx5/mlx5_rxtx.c
@@ -29,6 +29,7 @@ 
 #include <rte_flow.h>
 
 #include "mlx5.h"
+#include "mlx5_devx_cmds.h"
 #include "mlx5_utils.h"
 #include "mlx5_rxtx.h"
 #include "mlx5_autoconf.h"
diff --git a/drivers/net/mlx5/mlx5_txq.c b/drivers/net/mlx5/mlx5_txq.c
index 1a76f6e..5adb4dc 100644
--- a/drivers/net/mlx5/mlx5_txq.c
+++ b/drivers/net/mlx5/mlx5_txq.c
@@ -34,6 +34,7 @@ 
 #include "mlx5_rxtx.h"
 #include "mlx5_autoconf.h"
 #include "mlx5_glue.h"
+#include "mlx5_devx_cmds.h"
 
 /**
  * Allocate TX queue elements.
diff --git a/drivers/net/mlx5/mlx5_vlan.c b/drivers/net/mlx5/mlx5_vlan.c
index 5f6554a..feac0f1 100644
--- a/drivers/net/mlx5/mlx5_vlan.c
+++ b/drivers/net/mlx5/mlx5_vlan.c
@@ -30,6 +30,7 @@ 
 #include "mlx5.h"
 #include "mlx5_autoconf.h"
 #include "mlx5_glue.h"
+#include "mlx5_devx_cmds.h"
 #include "mlx5_rxtx.h"
 #include "mlx5_utils.h"