From patchwork Sat Jan 18 10:49:05 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anoob Joseph X-Patchwork-Id: 64863 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 41A88A051C; Sat, 18 Jan 2020 11:50:36 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id BE8F02C5E; Sat, 18 Jan 2020 11:50:26 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by dpdk.org (Postfix) with ESMTP id 265F12C5E for ; Sat, 18 Jan 2020 11:50:25 +0100 (CET) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 00IAkutt017647; Sat, 18 Jan 2020 02:50:24 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0818; bh=t5C4uavmUSFIi0SyCoMXuQi5S82GRkglpVh0MoDhjAs=; b=AzcmB+gBhXtFdrr9hZIX3zQbUrOZD7Z5UA4cAIcrzPNqrAgqmt20mehIBLXAEqsbBNKl LEgutTRN89n5sEhImZnxn1qEtOJG+Pg5NkJL1Fn7iYugwBmBhnuKhdlgis0Mxg2ixijt 6hhorljrlBo0Zi4U6uQFKmOHImgdT3AbU8EaqCqQH3N9be4zSFYCItOPC4QeNPzAuFIE mL1EkqO9cCyiTlwnle91CXvvIpAfDOoZxAphH9ZGDdchuKJj7hjM0fQu26HMTxThOnk6 udi9QzZgNEHvVWWFTlZUHUs8jTQosBAeZ8Nr+oubdWH1i5jmSpo1I96KyTSJjYgpa6QU cg== Received: from sc-exch01.marvell.com ([199.233.58.181]) by mx0b-0016f401.pphosted.com with ESMTP id 2xk0sn6egk-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Sat, 18 Jan 2020 02:50:24 -0800 Received: from SC-EXCH03.marvell.com (10.93.176.83) by SC-EXCH01.marvell.com (10.93.176.81) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Sat, 18 Jan 2020 02:50:22 -0800 Received: from maili.marvell.com (10.93.176.43) by SC-EXCH03.marvell.com (10.93.176.83) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Sat, 18 Jan 2020 02:50:22 -0800 Received: from ajoseph83.caveonetworks.com (unknown [10.29.45.60]) by maili.marvell.com (Postfix) with ESMTP id DC7253F7048; Sat, 18 Jan 2020 02:50:17 -0800 (PST) From: Anoob Joseph To: Akhil Goyal , Declan Doherty , Thomas Monjalon CC: Anoob Joseph , Jerin Jacob , Narayana Prasad , Kiran Kumar K , Nithin Dabilpuram , "Pavan Nikhilesh" , Ankur Dwivedi , Archana Muniganti , Tejasree Kondoj , Vamsi Attunuru , "Lukasz Bartosik" , Date: Sat, 18 Jan 2020 16:19:05 +0530 Message-ID: <1579344553-11428-8-git-send-email-anoobj@marvell.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1579344553-11428-1-git-send-email-anoobj@marvell.com> References: <1575806094-28391-1-git-send-email-anoobj@marvell.com> <1579344553-11428-1-git-send-email-anoobj@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.138, 18.0.572 definitions=2020-01-18_02:2020-01-16, 2020-01-18 signatures=0 Subject: [dpdk-dev] [PATCH v2 07/15] crypto/octeontx2: enable CPT to share QP with ethdev X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Adding the infrastructure to save one opaque pointer in idev and implement the consumer-producer in the PMDs which uses it accordingly. Signed-off-by: Ankur Dwivedi Signed-off-by: Anoob Joseph Signed-off-by: Archana Muniganti Signed-off-by: Tejasree Kondoj Signed-off-by: Vamsi Attunuru --- .../crypto/octeontx2/otx2_cryptodev_hw_access.h | 22 +---- drivers/crypto/octeontx2/otx2_cryptodev_ops.c | 18 ++++ drivers/crypto/octeontx2/otx2_cryptodev_qp.h | 35 ++++++++ drivers/crypto/octeontx2/otx2_security.c | 98 ++++++++++++++++++++++ drivers/crypto/octeontx2/otx2_security.h | 20 +++++ 5 files changed, 172 insertions(+), 21 deletions(-) create mode 100644 drivers/crypto/octeontx2/otx2_cryptodev_qp.h diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.h b/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.h index 6f78aa4..43db6a6 100644 --- a/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.h +++ b/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.h @@ -15,6 +15,7 @@ #include "cpt_mcode_defines.h" #include "otx2_dev.h" +#include "otx2_cryptodev_qp.h" /* CPT instruction queue length */ #define OTX2_CPT_IQ_LEN 8200 @@ -135,27 +136,6 @@ enum cpt_9x_comp_e { CPT_9X_COMP_E_LAST_ENTRY = 0x06 }; -struct otx2_cpt_qp { - uint32_t id; - /**< Queue pair id */ - uintptr_t base; - /**< Base address where BAR is mapped */ - void *lmtline; - /**< Address of LMTLINE */ - rte_iova_t lf_nq_reg; - /**< LF enqueue register address */ - struct pending_queue pend_q; - /**< Pending queue */ - struct rte_mempool *sess_mp; - /**< Session mempool */ - struct rte_mempool *sess_mp_priv; - /**< Session private data mempool */ - struct cpt_qp_meta_info meta_info; - /**< Metabuf info required to support operations on the queue pair */ - rte_iova_t iq_dma_addr; - /**< Instruction queue address */ -}; - void otx2_cpt_err_intr_unregister(const struct rte_cryptodev *dev); int otx2_cpt_err_intr_register(const struct rte_cryptodev *dev); diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_ops.c b/drivers/crypto/octeontx2/otx2_cryptodev_ops.c index b45cb82..d275478 100644 --- a/drivers/crypto/octeontx2/otx2_cryptodev_ops.c +++ b/drivers/crypto/octeontx2/otx2_cryptodev_ops.c @@ -13,6 +13,7 @@ #include "otx2_cryptodev_hw_access.h" #include "otx2_cryptodev_mbox.h" #include "otx2_cryptodev_ops.h" +#include "otx2_security.h" #include "otx2_mbox.h" #include "cpt_hw_types.h" @@ -148,6 +149,11 @@ otx2_cpt_qp_inline_cfg(const struct rte_cryptodev *dev, struct otx2_cpt_qp *qp) if (ret) return ret; + /* Publish inline Tx QP to eth dev security */ + ret = otx2_sec_tx_cpt_qp_add(port_id, qp); + if (ret) + return ret; + return 0; } @@ -242,6 +248,12 @@ otx2_cpt_qp_create(const struct rte_cryptodev *dev, uint16_t qp_id, qp->lf_nq_reg = qp->base + OTX2_CPT_LF_NQ(0); + ret = otx2_sec_tx_cpt_qp_remove(qp); + if (ret && (ret != -ENOENT)) { + CPT_LOG_ERR("Could not delete inline configuration"); + goto mempool_destroy; + } + otx2_cpt_iq_disable(qp); ret = otx2_cpt_qp_inline_cfg(dev, qp); @@ -275,6 +287,12 @@ otx2_cpt_qp_destroy(const struct rte_cryptodev *dev, struct otx2_cpt_qp *qp) char name[RTE_MEMZONE_NAMESIZE]; int ret; + ret = otx2_sec_tx_cpt_qp_remove(qp); + if (ret && (ret != -ENOENT)) { + CPT_LOG_ERR("Could not delete inline configuration"); + return ret; + } + otx2_cpt_iq_disable(qp); otx2_cpt_metabuf_mempool_destroy(qp); diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_qp.h b/drivers/crypto/octeontx2/otx2_cryptodev_qp.h new file mode 100644 index 0000000..9d48da4 --- /dev/null +++ b/drivers/crypto/octeontx2/otx2_cryptodev_qp.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright (C) 2020 Marvell International Ltd. + */ + +#ifndef _OTX2_CRYPTODEV_QP_H_ +#define _OTX2_CRYPTODEV_QP_H_ + +#include +#include +#include + +#include "cpt_common.h" + +struct otx2_cpt_qp { + uint32_t id; + /**< Queue pair id */ + uintptr_t base; + /**< Base address where BAR is mapped */ + void *lmtline; + /**< Address of LMTLINE */ + rte_iova_t lf_nq_reg; + /**< LF enqueue register address */ + struct pending_queue pend_q; + /**< Pending queue */ + struct rte_mempool *sess_mp; + /**< Session mempool */ + struct rte_mempool *sess_mp_priv; + /**< Session private data mempool */ + struct cpt_qp_meta_info meta_info; + /**< Metabuf info required to support operations on the queue pair */ + rte_iova_t iq_dma_addr; + /**< Instruction queue address */ +}; + +#endif /* _OTX2_CRYPTODEV_QP_H_ */ diff --git a/drivers/crypto/octeontx2/otx2_security.c b/drivers/crypto/octeontx2/otx2_security.c index b8c8f91..0534154 100644 --- a/drivers/crypto/octeontx2/otx2_security.c +++ b/drivers/crypto/octeontx2/otx2_security.c @@ -10,6 +10,7 @@ #include #include +#include "otx2_cryptodev_qp.h" #include "otx2_ethdev.h" #include "otx2_ipsec_fp.h" #include "otx2_security.h" @@ -29,6 +30,8 @@ struct sec_eth_tag_const { }; }; +static struct otx2_sec_eth_cfg sec_cfg[OTX2_MAX_INLINE_PORTS]; + static struct rte_cryptodev_capabilities otx2_sec_eth_crypto_caps[] = { { /* AES GCM */ .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC, @@ -116,16 +119,41 @@ static struct rte_security_ops otx2_sec_eth_ops = { .capabilities_get = otx2_sec_eth_capabilities_get }; +static int +otx2_sec_eth_cfg_init(int port_id) +{ + struct otx2_sec_eth_cfg *cfg; + int i; + + cfg = &sec_cfg[port_id]; + cfg->tx_cpt_idx = 0; + rte_spinlock_init(&cfg->tx_cpt_lock); + + for (i = 0; i < OTX2_MAX_CPT_QP_PER_PORT; i++) { + cfg->tx_cpt[i].qp = NULL; + rte_atomic16_set(&cfg->tx_cpt[i].ref_cnt, 0); + } + + return 0; +} + int otx2_sec_eth_ctx_create(struct rte_eth_dev *eth_dev) { struct rte_security_ctx *ctx; + int ret; ctx = rte_malloc("otx2_sec_eth_ctx", sizeof(struct rte_security_ctx), 0); if (ctx == NULL) return -ENOMEM; + ret = otx2_sec_eth_cfg_init(eth_dev->data->port_id); + if (ret) { + rte_free(ctx); + return ret; + } + /* Populate ctx */ ctx->device = eth_dev; @@ -239,3 +267,73 @@ otx2_sec_eth_fini(struct rte_eth_dev *eth_dev) in_sa_mz_name_get(name, RTE_MEMZONE_NAMESIZE, port); rte_memzone_free(rte_memzone_lookup(name)); } + +int +otx2_sec_tx_cpt_qp_add(uint16_t port_id, struct otx2_cpt_qp *qp) +{ + struct otx2_sec_eth_cfg *cfg; + int i, ret; + + if (qp == NULL || port_id > OTX2_MAX_INLINE_PORTS) + return -EINVAL; + + cfg = &sec_cfg[port_id]; + + /* Find a free slot to save CPT LF */ + + rte_spinlock_lock(&cfg->tx_cpt_lock); + + for (i = 0; i < OTX2_MAX_CPT_QP_PER_PORT; i++) { + if (cfg->tx_cpt[i].qp == NULL) { + cfg->tx_cpt[i].qp = qp; + ret = 0; + goto unlock; + } + } + + ret = -EINVAL; + +unlock: + rte_spinlock_unlock(&cfg->tx_cpt_lock); + return ret; +} + +int +otx2_sec_tx_cpt_qp_remove(struct otx2_cpt_qp *qp) +{ + struct otx2_sec_eth_cfg *cfg; + uint16_t port_id; + int i, ret; + + if (qp == NULL) + return -EINVAL; + + for (port_id = 0; port_id < OTX2_MAX_INLINE_PORTS; port_id++) { + cfg = &sec_cfg[port_id]; + + rte_spinlock_lock(&cfg->tx_cpt_lock); + + for (i = 0; i < OTX2_MAX_CPT_QP_PER_PORT; i++) { + if (cfg->tx_cpt[i].qp != qp) + continue; + + /* Don't free if the QP is in use by any sec session */ + if (rte_atomic16_read(&cfg->tx_cpt[i].ref_cnt)) { + ret = -EBUSY; + } else { + cfg->tx_cpt[i].qp = NULL; + ret = 0; + } + + goto unlock; + } + + rte_spinlock_unlock(&cfg->tx_cpt_lock); + } + + return -ENOENT; + +unlock: + rte_spinlock_unlock(&cfg->tx_cpt_lock); + return ret; +} diff --git a/drivers/crypto/octeontx2/otx2_security.h b/drivers/crypto/octeontx2/otx2_security.h index a442f5c..6086efa 100644 --- a/drivers/crypto/octeontx2/otx2_security.h +++ b/drivers/crypto/octeontx2/otx2_security.h @@ -5,10 +5,27 @@ #ifndef __OTX2_SECURITY_H__ #define __OTX2_SECURITY_H__ +#include #include +#include #include "otx2_ipsec_fp.h" +#define OTX2_MAX_CPT_QP_PER_PORT 64 +#define OTX2_MAX_INLINE_PORTS 64 + +struct otx2_cpt_qp; + +struct otx2_sec_eth_cfg { + struct { + struct otx2_cpt_qp *qp; + rte_atomic16_t ref_cnt; + } tx_cpt[OTX2_MAX_CPT_QP_PER_PORT]; + + uint16_t tx_cpt_idx; + rte_spinlock_t tx_cpt_lock; +}; + /* * Security session for inline IPsec protocol offload. This is private data of * inline capable PMD. @@ -33,4 +50,7 @@ int otx2_sec_eth_init(struct rte_eth_dev *eth_dev); void otx2_sec_eth_fini(struct rte_eth_dev *eth_dev); +int otx2_sec_tx_cpt_qp_add(uint16_t port_id, struct otx2_cpt_qp *qp); + +int otx2_sec_tx_cpt_qp_remove(struct otx2_cpt_qp *qp); #endif /* __OTX2_SECURITY_H__ */