[v2] net/mlx5: fix matcher field usage for metadata entities
diff mbox series

Message ID 1579259766-5445-1-git-send-email-viacheslavo@mellanox.com
State Accepted
Delegated to: Ferruh Yigit
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Series
  • [v2] net/mlx5: fix matcher field usage for metadata entities
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Commit Message

Slava Ovsiienko Jan. 17, 2020, 11:16 a.m. UTC
Matcher is flow table related structure providing the flow pattern
to be translated directly in hardware controlling data. This structure
includes the metadata register c0 field, that might be engaged to
support META and MARK related flow items and actions. Also, this
register might be used by kernel to specify the source vport index.
In this case (if kernel uses the field) the register c0 is split
into two 16-bit subfields - one for META/MARK items and another
to handle vport.

The actual configuration is queried by PMD from kernel in runtime
and depending on the mask returned by kernel the PMD can use upper
or lower half of register c0 field. This patch adds the missing
support for upper half. This missed support caused the non-operational
META/MARK items on some kernel configurations.

Fixes: e554b672aa05 ("net/mlx5: support flow tag")
Cc: stable@dpdk.org

Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
---
v1: http://patches.dpdk.org/patch/64069/
v2: - update log message
    - update headline from:
      "net/mlx5: fix register c0 usage for metadata entities"

 drivers/net/mlx5/mlx5_flow_dv.c | 39 +++++++++++++++++++++++++++++++++++----
 1 file changed, 35 insertions(+), 4 deletions(-)

Comments

Ferruh Yigit Jan. 17, 2020, 5:18 p.m. UTC | #1
On 1/17/2020 11:16 AM, Viacheslav Ovsiienko wrote:
> Matcher is flow table related structure providing the flow pattern
> to be translated directly in hardware controlling data. This structure
> includes the metadata register c0 field, that might be engaged to
> support META and MARK related flow items and actions. Also, this
> register might be used by kernel to specify the source vport index.
> In this case (if kernel uses the field) the register c0 is split
> into two 16-bit subfields - one for META/MARK items and another
> to handle vport.
> 
> The actual configuration is queried by PMD from kernel in runtime
> and depending on the mask returned by kernel the PMD can use upper
> or lower half of register c0 field. This patch adds the missing
> support for upper half. This missed support caused the non-operational
> META/MARK items on some kernel configurations.
> 
> Fixes: e554b672aa05 ("net/mlx5: support flow tag")
> Cc: stable@dpdk.org
> 
> Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
> Acked-by: Matan Azrad <matan@mellanox.com>
> ---
> v1: http://patches.dpdk.org/patch/64069/
> v2: - update log message
>     - update headline from:
>       "net/mlx5: fix register c0 usage for metadata entities"

Applied to dpdk-next-net/master, thanks.

Patch
diff mbox series

diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c
index 2b70788..dd21bc6 100644
--- a/drivers/net/mlx5/mlx5_flow_dv.c
+++ b/drivers/net/mlx5/mlx5_flow_dv.c
@@ -1088,6 +1088,14 @@  struct field_modify_info modify_tcp[] = {
 	if (reg < 0)
 		return reg;
 	assert(reg > 0);
+	if (reg == REG_C_0) {
+		uint32_t msk_c0 = priv->sh->dv_regc0_mask;
+		uint32_t shl_c0 = rte_bsf32(msk_c0);
+
+		data = rte_cpu_to_be_32(rte_cpu_to_be_32(data) << shl_c0);
+		mask = rte_cpu_to_be_32(mask) & msk_c0;
+		mask = rte_cpu_to_be_32(mask << shl_c0);
+	}
 	reg_c_x[0].id = reg_to_field[reg];
 	return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
 					     MLX5_MODIFICATION_TYPE_SET, error);
@@ -5842,6 +5850,15 @@  struct field_modify_info modify_tcp[] = {
 		/* Get the metadata register index for the mark. */
 		reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, NULL);
 		assert(reg > 0);
+		if (reg == REG_C_0) {
+			struct mlx5_priv *priv = dev->data->dev_private;
+			uint32_t msk_c0 = priv->sh->dv_regc0_mask;
+			uint32_t shl_c0 = rte_bsf32(msk_c0);
+
+			mask &= msk_c0;
+			mask <<= shl_c0;
+			value <<= shl_c0;
+		}
 		flow_dv_match_meta_reg(matcher, key, reg, value, mask);
 	}
 }
@@ -5923,6 +5940,8 @@  struct field_modify_info modify_tcp[] = {
 /**
  * Add tag item to matcher
  *
+ * @param[in] dev
+ *   The devich to configure through.
  * @param[in, out] matcher
  *   Flow matcher.
  * @param[in, out] key
@@ -5931,15 +5950,27 @@  struct field_modify_info modify_tcp[] = {
  *   Flow pattern to translate.
  */
 static void
-flow_dv_translate_mlx5_item_tag(void *matcher, void *key,
+flow_dv_translate_mlx5_item_tag(struct rte_eth_dev *dev,
+				void *matcher, void *key,
 				const struct rte_flow_item *item)
 {
 	const struct mlx5_rte_flow_item_tag *tag_v = item->spec;
 	const struct mlx5_rte_flow_item_tag *tag_m = item->mask;
+	uint32_t mask, value;
 
 	assert(tag_v);
-	flow_dv_match_meta_reg(matcher, key, tag_v->id, tag_v->data,
-			       tag_m ? tag_m->data : UINT32_MAX);
+	value = tag_v->data;
+	mask = tag_m ? tag_m->data : UINT32_MAX;
+	if (tag_v->id == REG_C_0) {
+		struct mlx5_priv *priv = dev->data->dev_private;
+		uint32_t msk_c0 = priv->sh->dv_regc0_mask;
+		uint32_t shl_c0 = rte_bsf32(msk_c0);
+
+		mask &= msk_c0;
+		mask <<= shl_c0;
+		value <<= shl_c0;
+	}
+	flow_dv_match_meta_reg(matcher, key, tag_v->id, value, mask);
 }
 
 /**
@@ -7286,7 +7317,7 @@  struct field_modify_info modify_tcp[] = {
 			last_item = MLX5_FLOW_ITEM_TAG;
 			break;
 		case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
-			flow_dv_translate_mlx5_item_tag(match_mask,
+			flow_dv_translate_mlx5_item_tag(dev, match_mask,
 							match_value, items);
 			last_item = MLX5_FLOW_ITEM_TAG;
 			break;