From patchwork Wed Dec 18 06:00:04 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joyce Kong X-Patchwork-Id: 63982 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id D2F3AA050F; Wed, 18 Dec 2019 07:00:59 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 9F3DF37B0; Wed, 18 Dec 2019 07:00:49 +0100 (CET) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by dpdk.org (Postfix) with ESMTP id 964D11B9BF for ; Wed, 18 Dec 2019 07:00:47 +0100 (CET) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 223311FB; Tue, 17 Dec 2019 22:00:47 -0800 (PST) Received: from net-arm-thunderx2-01.test.ast.arm.com (net-arm-thunderx2-01.shanghai.arm.com [10.169.40.68]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 47D683F718; Tue, 17 Dec 2019 22:00:42 -0800 (PST) From: Joyce Kong To: thomas@monjalon.net, stephen@networkplumber.org, david.marchand@redhat.com, mb@smartsharesystems.com, jerinj@marvell.com, bruce.richardson@intel.com, ravi1.kumar@amd.com, rmody@marvell.com, shshaikh@marvell.com, xuanziyang2@huawei.com, cloud.wangxiaoyun@huawei.com, zhouguoyang@huawei.com, honnappa.nagarahalli@arm.com, phil.yang@arm.com, gavin.hu@arm.com Cc: nd@arm.com, dev@dpdk.org Date: Wed, 18 Dec 2019 14:00:04 +0800 Message-Id: <1576648808-24765-3-git-send-email-joyce.kong@arm.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1576648808-24765-1-git-send-email-joyce.kong@arm.com> References: <1576648808-24765-1-git-send-email-joyce.kong@arm.com> In-Reply-To: <1571125801-45773-1-git-send-email-joyce.kong@arm.com> References: <1571125801-45773-1-git-send-email-joyce.kong@arm.com> Subject: [dpdk-dev] [PATCH v6 2/6] test/bitops: add bit operation test case X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add test cases for set bit, clear bit, test and set bit, test and clear bit operations. Signed-off-by: Joyce Kong Reviewed-by: Gavin Hu Reviewed-by: Phil Yang --- app/test/Makefile | 1 + app/test/autotest_data.py | 6 + app/test/meson.build | 2 + app/test/test_bitops.c | 305 ++++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 314 insertions(+) create mode 100644 app/test/test_bitops.c diff --git a/app/test/Makefile b/app/test/Makefile index 57930c0..4f33274 100644 --- a/app/test/Makefile +++ b/app/test/Makefile @@ -70,6 +70,7 @@ SRCS-y += test_ticketlock.c SRCS-y += test_memory.c SRCS-y += test_memzone.c SRCS-y += test_bitmap.c +SRCS-y += test_bitops.c SRCS-y += test_reciprocal_division.c SRCS-y += test_reciprocal_division_perf.c SRCS-y += test_fbarray.c diff --git a/app/test/autotest_data.py b/app/test/autotest_data.py index 6deb97b..7db2df1 100644 --- a/app/test/autotest_data.py +++ b/app/test/autotest_data.py @@ -405,6 +405,12 @@ "Report": None, }, { + "Name": "Bitops test", + "Command": "bitops_autotest", + "Func": default_autotest, + "Report": None, + }, + { "Name": "Hash multiwriter autotest", "Command": "hash_multiwriter_autotest", "Func": default_autotest, diff --git a/app/test/meson.build b/app/test/meson.build index fb49d80..ef340ca 100644 --- a/app/test/meson.build +++ b/app/test/meson.build @@ -14,6 +14,7 @@ test_sources = files('commands.c', 'test_atomic.c', 'test_barrier.c', 'test_bitratestats.c', + 'test_bitops.c', 'test_bpf.c', 'test_byteorder.c', 'test_cmdline.c', @@ -167,6 +168,7 @@ fast_test_names = [ 'alarm_autotest', 'atomic_autotest', 'byteorder_autotest', + 'bitops_autotest', 'cmdline_autotest', 'common_autotest', 'cpuflags_autotest', diff --git a/app/test/test_bitops.c b/app/test/test_bitops.c new file mode 100644 index 0000000..2a648aa --- /dev/null +++ b/app/test/test_bitops.c @@ -0,0 +1,305 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2019 Arm Limited + */ + +#include +#include +#include "test.h" + +uint32_t val32; +uint64_t val64; +unsigned int synchro; +unsigned int count32; +unsigned int count64; + +#define MAX_BITS_32 32 +#define MAX_BITS_64 64 +/* + * Bitops functions + * ================ + * + * - The main test function performs several subtests. + * - For relaxed version, check bit operations on one core. + * - Initialize valXX to specified values, then set each bit of valXX + * to 1 one by one in "test_bitops_set_relaxed". + * + * - Clear each bit of valXX to 0 one by one in "test_bitops_clear_relaxed". + * + * - Function "test_bitops_test_set_clear_relaxed" checks whether each bit + * of valXX can do "test and set" and "test and clear" correctly. + * + * - For C11 atomic barrier version, check bit operations on multi cores. + * - Per bit of valXX is set to 1, then cleared to 0 on each core in + * "test_bitops_set_clear". The function checks that once all lcores finish + * their set_clear, the value of valXX would still be zero. + * + * - The cores are waiting for a synchro which is triggered by the main test + * function. Then all cores would do "rte_test_and_set_bitXX" or + * "rte_test_and_clear_bitXX" at the same time, "countXX" which is checked + * as the result later would inc by one or not according to the original + * bit value. + * + */ + +static int +test_bitops_set_relaxed(void) +{ + unsigned int i; + + for (i = 0; i < MAX_BITS_32; i++) + rte_set_bit32_relaxed(i, &val32); + + for (i = 0; i < MAX_BITS_32; i++) + if (!rte_get_bit32_relaxed(i, &val32)) { + printf("Failed to set bit in relaxed version.\n"); + return TEST_FAILED; + } + + for (i = 0; i < MAX_BITS_64; i++) + rte_set_bit64_relaxed(i, &val64); + + for (i = 0; i < MAX_BITS_64; i++) + if (!rte_get_bit64_relaxed(i, &val64)) { + printf("Failed to set bit in relaxed version.\n"); + return TEST_FAILED; + } + + return TEST_SUCCESS; +} + +static int +test_bitops_clear_relaxed(void) +{ + unsigned int i; + + for (i = 0; i < MAX_BITS_32; i++) + rte_clear_bit32_relaxed(i, &val32); + + for (i = 0; i < MAX_BITS_32; i++) + if (rte_get_bit32_relaxed(i, &val32)) { + printf("Failed to clear bit in relaxed version.\n"); + return TEST_FAILED; + } + + for (i = 0; i < MAX_BITS_64; i++) + rte_clear_bit64_relaxed(i, &val64); + + for (i = 0; i < MAX_BITS_64; i++) + if (rte_get_bit64_relaxed(i, &val64)) { + printf("Failed to clear bit in relaxed version.\n"); + return TEST_FAILED; + } + + return TEST_SUCCESS; +} + +static int +test_bitops_test_set_clear_relaxed(void) +{ + unsigned int i; + + for (i = 0; i < MAX_BITS_32; i++) + rte_test_and_set_bit32_relaxed(i, &val32); + + for (i = 0; i < MAX_BITS_32; i++) + if (!rte_test_and_clear_bit32_relaxed(i, &val32)) { + printf("Failed to set and test bit in relaxed version.\n"); + return TEST_FAILED; + } + + for (i = 0; i < MAX_BITS_32; i++) + if (rte_get_bit32_relaxed(i, &val32)) { + printf("Failed to test and clear bit in relaxed version.\n"); + return TEST_FAILED; + } + + for (i = 0; i < MAX_BITS_64; i++) + rte_test_and_set_bit64_relaxed(i, &val64); + + for (i = 0; i < MAX_BITS_64; i++) + if (!rte_test_and_clear_bit64_relaxed(i, &val64)) { + printf("Failed to set and test bit in relaxed version.\n"); + return TEST_FAILED; + } + + for (i = 0; i < MAX_BITS_64; i++) + if (rte_get_bit64_relaxed(i, &val64)) { + printf("Failed to test and clear bit in relaxed version.\n"); + return TEST_FAILED; + } + + return TEST_SUCCESS; +} + +static int +test_bitops_set_clear(__attribute__((unused)) void *arg) +{ + while (__atomic_load_n(&synchro, __ATOMIC_RELAXED) == 0) + ; + + unsigned int i; + + for (i = 0; i < MAX_BITS_32; i++) + rte_set_bit32(i, &val32); + for (i = 0; i < MAX_BITS_32; i++) + rte_clear_bit32(i, &val32); + + for (i = 0; i < MAX_BITS_64; i++) + rte_set_bit64(i, &val64); + for (i = 0; i < MAX_BITS_64; i++) + rte_clear_bit64(i, &val64); + + return TEST_SUCCESS; +} + +/* + * rte_test_and_set_bitXX() returns the original bit value, then set it to 1. + * This functions checks that if the target bit is equal to 0, set it to 1 and + * increase the variable of "countXX" by one. If it is equal to 1, do nothing + * for "countXX". The value of "countXX" would be checked as the result later. + */ +static int +test_bitops_test_set(__attribute__((unused)) void *arg) + +{ + while (__atomic_load_n(&synchro, __ATOMIC_RELAXED) == 0) + ; + + unsigned int i; + + for (i = 0; i < MAX_BITS_32; i++) + if (!rte_test_and_set_bit32(i, &val32)) + __atomic_fetch_add(&count32, 1, __ATOMIC_ACQ_REL); + + for (i = 0; i < MAX_BITS_64; i++) + if (!rte_test_and_set_bit64(i, &val64)) + __atomic_fetch_add(&count64, 1, __ATOMIC_ACQ_REL); + + return TEST_SUCCESS; +} + +/* + * rte_test_and_set_bitXX() returns the original bit value, then clear it to 0. + * This functions checks that if the target bit is equal to 1, clear it to 0 and + * increase the variable of "countXX" by one. If it is equal to 0, do nothing + * for "countXX". The value of "countXX" would be checked as the result later. + */ +static int +test_bitops_test_clear(__attribute__((unused)) void *arg) + +{ + while (__atomic_load_n(&synchro, __ATOMIC_RELAXED) == 0) + ; + + unsigned int i; + + for (i = 0; i < MAX_BITS_32; i++) + if (rte_test_and_clear_bit32(i, &val32)) + __atomic_fetch_add(&count32, 1, __ATOMIC_ACQ_REL); + + for (i = 0; i < MAX_BITS_64; i++) + if (rte_test_and_clear_bit64(i, &val64)) + __atomic_fetch_add(&count64, 1, __ATOMIC_ACQ_REL); + + return TEST_SUCCESS; +} + +static int +test_bitops(void) +{ + __atomic_store_n(&val32, 0, __ATOMIC_RELAXED); + __atomic_store_n(&val64, 0, __ATOMIC_RELAXED); + __atomic_store_n(&synchro, 0, __ATOMIC_RELAXED); + __atomic_store_n(&count32, 0, __ATOMIC_RELAXED); + __atomic_store_n(&count64, 0, __ATOMIC_RELAXED); + + if (test_bitops_set_relaxed() < 0) + return TEST_FAILED; + + if (test_bitops_clear_relaxed() < 0) + return TEST_FAILED; + + if (test_bitops_test_set_clear_relaxed() < 0) + return TEST_FAILED; + + + rte_eal_mp_remote_launch(test_bitops_set_clear, NULL, SKIP_MASTER); + __atomic_store_n(&synchro, 1, __ATOMIC_RELAXED); + rte_eal_mp_wait_lcore(); + __atomic_store_n(&synchro, 0, __ATOMIC_RELAXED); + + unsigned int i; + + for (i = 0; i < MAX_BITS_32; i++) + if (rte_get_bit32(i, &val32)) { + printf("Failed to set and clear bit on multi cores.\n"); + return TEST_FAILED; + } + + for (i = 0; i < MAX_BITS_64; i++) + if (rte_get_bit64(i, &val64)) { + printf("Failed to set and clear bit on multi cores.\n"); + return TEST_FAILED; + } + + /* + * Launch all slave lcores to do "rte_bitops_test_and_set_bitXX" + * respectively. + * Each lcore should have MAX_BITS_XX chances to check the target bit. + * If it's equal to 0, set it to 1 and "countXX (which is initialized + * to 0)" would be increased by one. If the target bit is 1, still set + * it to 1 and do nothing for "countXX". There would be only one lcore + * that finds the target bit is 0. + * If the final value of "countXX" is equal to MAX_BITS_XX, all slave + * lcores performed "rte_bitops_test_and_set_bitXX" correctly. + */ + __atomic_store_n(&count32, 0, __ATOMIC_RELAXED); + __atomic_store_n(&count64, 0, __ATOMIC_RELAXED); + + rte_eal_mp_remote_launch(test_bitops_test_set, NULL, SKIP_MASTER); + __atomic_store_n(&synchro, 1, __ATOMIC_RELAXED); + rte_eal_mp_wait_lcore(); + __atomic_store_n(&synchro, 0, __ATOMIC_RELAXED); + + if (__atomic_load_n(&count32, __ATOMIC_RELAXED) != MAX_BITS_32) { + printf("Failed to test and set on multi cores.\n"); + return TEST_FAILED; + } + if (__atomic_load_n(&count64, __ATOMIC_RELAXED) != MAX_BITS_64) { + printf("Failed to test and set on multi cores.\n"); + return TEST_FAILED; + } + + /* + * Launch all slave lcores to do "rte_bitops_test_and_clear_bitXX" + * respectively. + * Each lcore should have MAX_BITS_XX chances to check the target bit. + * If it's equal to 1, clear it to 0 and "countXX (which is initialized + * to 0)" would be increased by one. If the target bit is 0, still clear + * it to 0 and do nothing for "countXX". There would be only one lcore + * that finds the target bit is 1. + * If the final value of "countXX" is equal to MAX_BITS_XX, all slave + * lcores performed "rte_bitops_test_and_clear_bitXX" correctly. + */ + + __atomic_store_n(&count32, 0, __ATOMIC_RELAXED); + __atomic_store_n(&count64, 0, __ATOMIC_RELAXED); + + rte_eal_mp_remote_launch(test_bitops_test_clear, NULL, SKIP_MASTER); + __atomic_store_n(&synchro, 1, __ATOMIC_RELAXED); + rte_eal_mp_wait_lcore(); + __atomic_store_n(&synchro, 0, __ATOMIC_RELAXED); + + if (__atomic_load_n(&count32, __ATOMIC_RELAXED) != MAX_BITS_32) { + printf("Failed to test and clear on multi cores.\n"); + return TEST_FAILED; + } + if (__atomic_load_n(&count64, __ATOMIC_RELAXED) != MAX_BITS_64) { + printf("Failed to test and clear on multi cores.\n"); + return TEST_FAILED; + } + + return TEST_SUCCESS; +} + +REGISTER_TEST_COMMAND(bitops_autotest, test_bitops);