From patchwork Wed Dec 18 06:00:03 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Joyce Kong X-Patchwork-Id: 63981 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id DE1B7A050E; Wed, 18 Dec 2019 07:00:46 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 685BA34EF; Wed, 18 Dec 2019 07:00:44 +0100 (CET) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by dpdk.org (Postfix) with ESMTP id 722B42C52 for ; Wed, 18 Dec 2019 07:00:42 +0100 (CET) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id CBDA131B; Tue, 17 Dec 2019 22:00:41 -0800 (PST) Received: from net-arm-thunderx2-01.test.ast.arm.com (net-arm-thunderx2-01.shanghai.arm.com [10.169.40.68]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 0A0BE3F718; Tue, 17 Dec 2019 22:00:36 -0800 (PST) From: Joyce Kong To: thomas@monjalon.net, stephen@networkplumber.org, david.marchand@redhat.com, mb@smartsharesystems.com, jerinj@marvell.com, bruce.richardson@intel.com, ravi1.kumar@amd.com, rmody@marvell.com, shshaikh@marvell.com, xuanziyang2@huawei.com, cloud.wangxiaoyun@huawei.com, zhouguoyang@huawei.com, honnappa.nagarahalli@arm.com, phil.yang@arm.com, gavin.hu@arm.com Cc: nd@arm.com, dev@dpdk.org Date: Wed, 18 Dec 2019 14:00:03 +0800 Message-Id: <1576648808-24765-2-git-send-email-joyce.kong@arm.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1576648808-24765-1-git-send-email-joyce.kong@arm.com> References: <1576648808-24765-1-git-send-email-joyce.kong@arm.com> In-Reply-To: <1571125801-45773-1-git-send-email-joyce.kong@arm.com> References: <1571125801-45773-1-git-send-email-joyce.kong@arm.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v6 1/6] lib/eal: implement the family of rte bit operation APIs X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" There are a lot functions of bit operations scattered and duplicated in PMDs, consolidating them into a common API family is necessary. Furthermore, when the bit operation is applied to the IO devices, use __ATOMIC_ACQ_REL to ensure the ordering for io bit operation. Signed-off-by: Joyce Kong Reviewed-by: Gavin Hu Reviewed-by: Phil Yang Acked-by: Morten Brørup --- MAINTAINERS | 5 + doc/api/doxy-api-index.md | 5 +- lib/librte_eal/common/Makefile | 1 + lib/librte_eal/common/include/rte_bitops.h | 474 +++++++++++++++++++++++++++++ lib/librte_eal/common/meson.build | 3 +- 5 files changed, 485 insertions(+), 3 deletions(-) create mode 100644 lib/librte_eal/common/include/rte_bitops.h diff --git a/MAINTAINERS b/MAINTAINERS index 4395d8d..d2a29a2 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -236,6 +236,11 @@ M: Cristian Dumitrescu F: lib/librte_eal/common/include/rte_bitmap.h F: app/test/test_bitmap.c +Bitops +M: Joyce Kong +F: lib/librte_eal/common/include/rte_bitops.h +F: app/test/test_bitops.c + MCSlock - EXPERIMENTAL M: Phil Yang F: lib/librte_eal/common/include/generic/rte_mcslock.h diff --git a/doc/api/doxy-api-index.md b/doc/api/doxy-api-index.md index dff496b..ade7c01 100644 --- a/doc/api/doxy-api-index.md +++ b/doc/api/doxy-api-index.md @@ -133,12 +133,13 @@ The public API headers are grouped by topics: [BPF] (@ref rte_bpf.h) - **containers**: + [bitmap] (@ref rte_bitmap.h), + [bitops] (@ref rte_bitops.h), [mbuf] (@ref rte_mbuf.h), [mbuf pool ops] (@ref rte_mbuf_pool_ops.h), [ring] (@ref rte_ring.h), [stack] (@ref rte_stack.h), - [tailq] (@ref rte_tailq.h), - [bitmap] (@ref rte_bitmap.h) + [tailq] (@ref rte_tailq.h) - **packet framework**: * [port] (@ref rte_port.h): diff --git a/lib/librte_eal/common/Makefile b/lib/librte_eal/common/Makefile index c2c6d92..dd025c1 100644 --- a/lib/librte_eal/common/Makefile +++ b/lib/librte_eal/common/Makefile @@ -19,6 +19,7 @@ INC += rte_malloc.h rte_keepalive.h rte_time.h INC += rte_service.h rte_service_component.h INC += rte_bitmap.h rte_vfio.h rte_hypervisor.h rte_test.h INC += rte_reciprocal.h rte_fbarray.h rte_uuid.h +INC += rte_bitops.h GENERIC_INC := rte_atomic.h rte_byteorder.h rte_cycles.h rte_prefetch.h GENERIC_INC += rte_memcpy.h rte_cpuflags.h diff --git a/lib/librte_eal/common/include/rte_bitops.h b/lib/librte_eal/common/include/rte_bitops.h new file mode 100644 index 0000000..34158d1 --- /dev/null +++ b/lib/librte_eal/common/include/rte_bitops.h @@ -0,0 +1,474 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2019 Arm Limited + */ + +#ifndef _RTE_BITOPS_H_ +#define _RTE_BITOPS_H_ + +/** + * @file + * Bit Operations + * + * This file defines a API for bit operations without/with memory ordering. + */ + +#include +#include +#include + +/*---------------------------- 32 bit operations ----------------------------*/ + +/** + * @warning + * @b EXPERIMENTAL: this API may change, or be removed, without prior notice + * + * Get the target bit from a 32-bit value without memory ordering. + * + * @param nr + * The target bit to get. + * @param addr + * The address holding the bit. + * @return + * The target bit. + */ +__rte_experimental +static inline uint32_t +rte_get_bit32_relaxed(unsigned int nr, uint32_t *addr) +{ + RTE_ASSERT(nr < 32); + + uint32_t mask = UINT32_C(1) << nr; + return __atomic_load_n(addr, __ATOMIC_RELAXED) & mask; +} + +/** + * @warning + * @b EXPERIMENTAL: this API may change, or be removed, without prior notice + * + * Set the target bit in a 32-bit value to 1 without memory ordering. + * + * @param nr + * The target bit to set. + * @param addr + * The address holding the bit. + */ +__rte_experimental +static inline void +rte_set_bit32_relaxed(unsigned int nr, uint32_t *addr) +{ + RTE_ASSERT(nr < 32); + + uint32_t mask = UINT32_C(1) << nr; + __atomic_fetch_or(addr, mask, __ATOMIC_RELAXED); +} + +/** + * @warning + * @b EXPERIMENTAL: this API may change, or be removed, without prior notice + * + * Clear the target bit in a 32-bit value to 0 without memory ordering. + * + * @param nr + * The target bit to clear. + * @param addr + * The address holding the bit. + */ +__rte_experimental +static inline void +rte_clear_bit32_relaxed(unsigned int nr, uint32_t *addr) +{ + RTE_ASSERT(nr < 32); + + uint32_t mask = UINT32_C(1) << nr; + __atomic_fetch_and(addr, ~mask, __ATOMIC_RELAXED); +} + +/** + * @warning + * @b EXPERIMENTAL: this API may change, or be removed, without prior notice + * + * Return the original bit from a 32-bit value, then set it to 1 without + * memory ordering. + * + * @param nr + * The target bit to get and set. + * @param addr + * The address holding the bit. + * @return + * The original bit. + */ +__rte_experimental +static inline uint32_t +rte_test_and_set_bit32_relaxed(unsigned int nr, uint32_t *addr) +{ + RTE_ASSERT(nr < 32); + + uint32_t mask = UINT32_C(1) << nr; + return __atomic_fetch_or(addr, mask, __ATOMIC_RELAXED) & mask; +} + +/** + * @warning + * @b EXPERIMENTAL: this API may change, or be removed, without prior notice + * + * Return the original bit from a 32-bit value, then clear it to 0 without + * memory ordering. + * + * @param nr + * The target bit to get and clear. + * @param addr + * The address holding the bit. + * @return + * The original bit. + */ +__rte_experimental +static inline uint32_t +rte_test_and_clear_bit32_relaxed(unsigned int nr, uint32_t *addr) +{ + RTE_ASSERT(nr < 32); + + uint32_t mask = UINT32_C(1) << nr; + return __atomic_fetch_and(addr, ~mask, __ATOMIC_RELAXED) & mask; +} + +/** + * @warning + * @b EXPERIMENTAL: this API may change, or be removed, without prior notice + * + * Get the target bit from a 32-bit value with memory ordering. + * + * @param nr + * The target bit to get. + * @param addr + * The address holding the bit. + * @return + * The target bit. + */ +__rte_experimental +static inline uint32_t +rte_get_bit32(unsigned int nr, uint32_t *addr) +{ + RTE_ASSERT(nr < 32); + + uint32_t mask = UINT32_C(1) << nr; + return __atomic_load_n(addr, __ATOMIC_ACQUIRE) & mask; +} + +/** + * @warning + * @b EXPERIMENTAL: this API may change, or be removed, without prior notice + * + * Set the target bit in a 32-bit value to 1 with memory ordering. + * + * @param nr + * The target bit to set. + * @param addr + * The address holding the bit. + */ +__rte_experimental +static inline void +rte_set_bit32(unsigned int nr, uint32_t *addr) +{ + RTE_ASSERT(nr < 32); + + uint32_t mask = UINT32_C(1) << nr; + __atomic_fetch_or(addr, mask, __ATOMIC_ACQ_REL); +} + +/** + * @warning + * @b EXPERIMENTAL: this API may change, or be removed, without prior notice + * + * Clear the target bit in a 32-bit value to 0 with memory ordering. + * + * @param nr + * The target bit to clear. + * @param addr + * The address holding the bit. + */ +__rte_experimental +static inline void +rte_clear_bit32(unsigned int nr, uint32_t *addr) +{ + RTE_ASSERT(nr < 32); + + uint32_t mask = UINT32_C(1) << nr; + __atomic_fetch_and(addr, ~mask, __ATOMIC_ACQ_REL); +} + +/** + * @warning + * @b EXPERIMENTAL: this API may change, or be removed, without prior notice + * + * Return the original bit from a 32-bit value, then set it to 1 with + * memory ordering. + * + * @param nr + * The target bit to get and set. + * @param addr + * The address holding the bit. + * @return + * The original bit. + */ +__rte_experimental +static inline uint32_t +rte_test_and_set_bit32(unsigned int nr, uint32_t *addr) +{ + RTE_ASSERT(nr < 32); + + uint32_t mask = UINT32_C(1) << nr; + return __atomic_fetch_or(addr, mask, __ATOMIC_ACQ_REL) & mask; +} + +/** + * @warning + * @b EXPERIMENTAL: this API may change, or be removed, without prior notice + * + * Return the original bit from a 32-bit value, then clear it to 0 with + * memory ordering. + * + * @param nr + * The target bit to get and clear. + * @param addr + * The address holding the bit. + * @return + * The original bit. + */ +__rte_experimental +static inline uint32_t +rte_test_and_clear_bit32(unsigned int nr, uint32_t *addr) +{ + RTE_ASSERT(nr < 32); + + uint32_t mask = UINT32_C(1) << nr; + return __atomic_fetch_and(addr, ~mask, __ATOMIC_ACQ_REL) & mask; +} + +/*---------------------------- 64 bit operations ----------------------------*/ + +/** + * @warning + * @b EXPERIMENTAL: this API may change, or be removed, without prior notice + * + * Get the target bit from a 64-bit value without memory ordering. + * + * @param nr + * The target bit to get. + * @param addr + * The address holding the bit. + * @return + * The target bit. + */ +__rte_experimental +static inline uint64_t +rte_get_bit64_relaxed(unsigned int nr, uint64_t *addr) +{ + RTE_ASSERT(nr < 64); + + uint64_t mask = UINT64_C(1) << nr; + return __atomic_load_n(addr, __ATOMIC_RELAXED) & mask; +} + +/** + * @warning + * @b EXPERIMENTAL: this API may change, or be removed, without prior notice + * + * Set the target bit in a 64-bit value to 1 without memory ordering. + * + * @param nr + * The target bit to set. + * @param addr + * The address holding the bit. + */ +__rte_experimental +static inline void +rte_set_bit64_relaxed(unsigned int nr, uint64_t *addr) +{ + RTE_ASSERT(nr < 64); + + uint64_t mask = UINT64_C(1) << nr; + __atomic_fetch_or(addr, mask, __ATOMIC_RELAXED); +} + +/** + * @warning + * @b EXPERIMENTAL: this API may change, or be removed, without prior notice + * + * Clear the target bit in a 64-bit value to 0 without memory ordering. + * + * @param nr + * The target bit to clear. + * @param addr + * The address holding the bit. + */ +__rte_experimental +static inline void +rte_clear_bit64_relaxed(unsigned int nr, uint64_t *addr) +{ + RTE_ASSERT(nr < 64); + + uint64_t mask = UINT64_C(1) << nr; + __atomic_fetch_and(addr, ~mask, __ATOMIC_RELAXED); +} + +/** + * @warning + * @b EXPERIMENTAL: this API may change, or be removed, without prior notice + * + * Return the original bit from a 64-bit value, then set it to 1 without + * memory ordering. + * + * @param nr + * The target bit to get and set. + * @param addr + * The address holding the bit. + * @return + * The original bit. + */ +__rte_experimental +static inline uint64_t +rte_test_and_set_bit64_relaxed(unsigned int nr, uint64_t *addr) +{ + RTE_ASSERT(nr < 64); + + uint64_t mask = UINT64_C(1) << nr; + return __atomic_fetch_or(addr, mask, __ATOMIC_RELAXED) & mask; +} + +/** + * @warning + * @b EXPERIMENTAL: this API may change, or be removed, without prior notice + * + * Return the original bit from a 64-bit value, then clear it to 0 without + * memory ordering. + * + * @param nr + * The target bit to get and clear. + * @param addr + * The address holding the bit. + * @return + * The original bit. + */ +__rte_experimental +static inline uint64_t +rte_test_and_clear_bit64_relaxed(unsigned int nr, uint64_t *addr) +{ + RTE_ASSERT(nr < 64); + + uint64_t mask = UINT64_C(1) << nr; + return __atomic_fetch_and(addr, ~mask, __ATOMIC_RELAXED) & mask; +} + +/** + * @warning + * @b EXPERIMENTAL: this API may change, or be removed, without prior notice + * + * Get the target bit from a 64-bit value with memory ordering. + * + * @param nr + * The target bit to get. + * @param addr + * The address holding the bit. + * @return + * The target bit. + */ +__rte_experimental +static inline uint64_t +rte_get_bit64(unsigned int nr, uint64_t *addr) +{ + RTE_ASSERT(nr < 64); + + uint64_t mask = UINT64_C(1) << nr; + return __atomic_load_n(addr, __ATOMIC_ACQUIRE) & mask; +} + +/** + * @warning + * @b EXPERIMENTAL: this API may change, or be removed, without prior notice + * + * Set the target bit in a 64-bit value to 1 with memory ordering. + * + * @param nr + * The target bit to set. + * @param addr + * The address holding the bit. + */ +__rte_experimental +static inline void +rte_set_bit64(unsigned int nr, uint64_t *addr) +{ + RTE_ASSERT(nr < 64); + + uint64_t mask = UINT64_C(1) << nr; + __atomic_fetch_or(addr, mask, __ATOMIC_ACQ_REL); +} + +/** + * @warning + * @b EXPERIMENTAL: this API may change, or be removed, without prior notice + * + * Clear the target bit in a 64-bit value to 0 with memory ordering. + * + * @param nr + * The target bit to clear. + * @param addr + * The address holding the bit. + */ +__rte_experimental +static inline void +rte_clear_bit64(unsigned int nr, uint64_t *addr) +{ + RTE_ASSERT(nr < 64); + + uint64_t mask = UINT64_C(1) << nr; + __atomic_fetch_and(addr, ~mask, __ATOMIC_ACQ_REL); +} + +/** + * @warning + * @b EXPERIMENTAL: this API may change, or be removed, without prior notice + * + * Return the original bit from a 64-bit value, then set it to 1 with + * memory ordering. + * + * @param nr + * The target bit to get and set. + * @param addr + * The address holding the bit. + * @return + * The original bit. + */ +__rte_experimental +static inline uint64_t +rte_test_and_set_bit64(unsigned int nr, uint64_t *addr) +{ + RTE_ASSERT(nr < 64); + + uint64_t mask = UINT64_C(1) << nr; + return __atomic_fetch_or(addr, mask, __ATOMIC_ACQ_REL) & mask; +} + +/** + * @warning + * @b EXPERIMENTAL: this API may change, or be removed, without prior notice + * + * Return the original bit from a 64-bit value, then clear it to 0 with + * memory ordering. + * + * @param nr + * The target bit to get and clear. + * @param addr + * The address holding the bit. + * @return + * The original bit. + */ +__rte_experimental +static inline uint64_t +rte_test_and_clear_bit64(unsigned int nr, uint64_t *addr) +{ + RTE_ASSERT(nr < 64); + + uint64_t mask = UINT64_C(1) << nr; + return __atomic_fetch_and(addr, ~mask, __ATOMIC_ACQ_REL) & mask; +} +#endif /* _RTE_BITOPS_H_ */ diff --git a/lib/librte_eal/common/meson.build b/lib/librte_eal/common/meson.build index 2b97715..766edbd 100644 --- a/lib/librte_eal/common/meson.build +++ b/lib/librte_eal/common/meson.build @@ -50,9 +50,10 @@ common_objs += eal_common_arch_objs common_headers = files( 'include/rte_alarm.h', + 'include/rte_bitmap.h', + 'include/rte_bitops.h', 'include/rte_branch_prediction.h', 'include/rte_bus.h', - 'include/rte_bitmap.h', 'include/rte_class.h', 'include/rte_common.h', 'include/rte_compat.h',