[14/69] net/i40e/base: adding flags for PHY types
diff mbox series

Message ID 20191202074935.97629-15-xiaolong.ye@intel.com
State New
Delegated to: xiaolong ye
Headers show
Series
  • update for i40e base code
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Checks

Context Check Description
ci/Intel-compilation success Compilation OK
ci/checkpatch success coding style OK

Commit Message

Ye Xiaolong Dec. 2, 2019, 7:48 a.m. UTC
Adding bit flags to enable/disable EEE capability on Carlsville HW
for 2.5GBase-T and 5GBase-T PHY types as well as 'Set autonomous
EEE for relevant enabled PHY types' flag.

Signed-off-by: Doug Dziggel <douglas.a.dziggel@intel.com>
Signed-off-by: Michal Litwicki <michalx.litwicki@intel.com>
Reviewed-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Reviewed-by: Michael Alice <alice.michael@intel.com>
Reviewed-by: Aleksandr Loktionov <aleksandr.loktionov@intel.com>
Signed-off-by: Xiaolong Ye <xiaolong.ye@intel.com>
---
 drivers/net/i40e/base/i40e_adminq_cmd.h | 7 +++++++
 1 file changed, 7 insertions(+)

Patch
diff mbox series

diff --git a/drivers/net/i40e/base/i40e_adminq_cmd.h b/drivers/net/i40e/base/i40e_adminq_cmd.h
index 4454bce5a..9179bbe8f 100644
--- a/drivers/net/i40e/base/i40e_adminq_cmd.h
+++ b/drivers/net/i40e/base/i40e_adminq_cmd.h
@@ -2027,12 +2027,19 @@  struct i40e_aq_get_phy_abilities_resp {
 #define I40E_AQ_PHY_FEC_ABILITY_KR	0x40
 #define I40E_AQ_PHY_FEC_ABILITY_RS	0x80
 	__le16	eee_capability;
+#ifdef CARLSVILLE_HW
+#define I40E_AQ_EEE_AUTO		0x0001
+#endif
 #define I40E_AQ_EEE_100BASE_TX		0x0002
 #define I40E_AQ_EEE_1000BASE_T		0x0004
 #define I40E_AQ_EEE_10GBASE_T		0x0008
 #define I40E_AQ_EEE_1000BASE_KX		0x0010
 #define I40E_AQ_EEE_10GBASE_KX4		0x0020
 #define I40E_AQ_EEE_10GBASE_KR		0x0040
+#ifdef CARLSVILLE_HW
+#define I40E_AQ_EEE_2_5GBASE_T		0x0100
+#define I40E_AQ_EEE_5GBASE_T		0x0200
+#endif
 	__le32	eeer_val;
 	u8	d3_lpan;
 #define I40E_AQ_SET_PHY_D3_LPAN_ENA	0x01