From patchwork Fri Sep 20 13:25:52 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Wei Hu (Xavier)" X-Patchwork-Id: 59519 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 3EDD31F47C; Fri, 20 Sep 2019 15:29:13 +0200 (CEST) Received: from huawei.com (szxga06-in.huawei.com [45.249.212.32]) by dpdk.org (Postfix) with ESMTP id 4F4CB1F40B for ; Fri, 20 Sep 2019 15:28:42 +0200 (CEST) Received: from DGGEMS412-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id 072BDFF03E2BDCC49220; Fri, 20 Sep 2019 21:28:41 +0800 (CST) Received: from localhost.localdomain (10.67.212.132) by DGGEMS412-HUB.china.huawei.com (10.3.19.212) with Microsoft SMTP Server id 14.3.439.0; Fri, 20 Sep 2019 21:28:32 +0800 From: "Wei Hu (Xavier)" To: CC: , , Date: Fri, 20 Sep 2019 21:25:52 +0800 Message-ID: <1568985955-13548-20-git-send-email-xavier.huwei@huawei.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1568985955-13548-1-git-send-email-xavier.huwei@huawei.com> References: <1568985955-13548-1-git-send-email-xavier.huwei@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.132] X-CFilter-Loop: Reflected Subject: [dpdk-dev] [PATCH v2 19/22] net/hns3: add abnormal interrupt process for hns3 PMD driver X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This patch adds abnormal interrupt process for hns3 PMD driver, the interrupt reported by NIC hardware. Signed-off-by: Chunsong Feng Signed-off-by: Min Hu (Connor) Signed-off-by: Wei Hu (Xavier) Signed-off-by: Hao Chen Signed-off-by: Huisong Li --- drivers/net/hns3/Makefile | 1 + drivers/net/hns3/hns3_ethdev.c | 164 ++++++++++ drivers/net/hns3/hns3_ethdev_vf.c | 9 +- drivers/net/hns3/hns3_intr.c | 654 ++++++++++++++++++++++++++++++++++++++ drivers/net/hns3/hns3_intr.h | 68 ++++ drivers/net/hns3/hns3_mbx.c | 1 + drivers/net/hns3/meson.build | 1 + 7 files changed, 897 insertions(+), 1 deletion(-) create mode 100644 drivers/net/hns3/hns3_intr.c create mode 100644 drivers/net/hns3/hns3_intr.h diff --git a/drivers/net/hns3/Makefile b/drivers/net/hns3/Makefile index 4cc971b..45a39b9 100644 --- a/drivers/net/hns3/Makefile +++ b/drivers/net/hns3/Makefile @@ -30,6 +30,7 @@ SRCS-$(CONFIG_RTE_LIBRTE_HNS3_PMD) += hns3_rxtx.c SRCS-$(CONFIG_RTE_LIBRTE_HNS3_PMD) += hns3_rss.c SRCS-$(CONFIG_RTE_LIBRTE_HNS3_PMD) += hns3_flow.c SRCS-$(CONFIG_RTE_LIBRTE_HNS3_PMD) += hns3_fdir.c +SRCS-$(CONFIG_RTE_LIBRTE_HNS3_PMD) += hns3_intr.c SRCS-$(CONFIG_RTE_LIBRTE_HNS3_PMD) += hns3_regs.c SRCS-$(CONFIG_RTE_LIBRTE_HNS3_PMD) += hns3_dcb.c diff --git a/drivers/net/hns3/hns3_ethdev.c b/drivers/net/hns3/hns3_ethdev.c index c8a6283..578a3de 100644 --- a/drivers/net/hns3/hns3_ethdev.c +++ b/drivers/net/hns3/hns3_ethdev.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -24,6 +25,7 @@ #include "hns3_ethdev.h" #include "hns3_logs.h" #include "hns3_rxtx.h" +#include "hns3_intr.h" #include "hns3_regs.h" #include "hns3_dcb.h" @@ -50,10 +52,136 @@ int hns3_logtype_init; int hns3_logtype_driver; +enum hns3_evt_cause { + HNS3_VECTOR0_EVENT_RST, + HNS3_VECTOR0_EVENT_MBX, + HNS3_VECTOR0_EVENT_ERR, + HNS3_VECTOR0_EVENT_OTHER, +}; + static int hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu); static int hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid, int on); +static void +hns3_pf_disable_irq0(struct hns3_hw *hw) +{ + hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0); +} + +static void +hns3_pf_enable_irq0(struct hns3_hw *hw) +{ + hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1); +} + +static enum hns3_evt_cause +hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval) +{ + struct hns3_hw *hw = &hns->hw; + uint32_t vector0_int_stats; + uint32_t cmdq_src_val; + uint32_t val; + enum hns3_evt_cause ret; + + /* fetch the events from their corresponding regs */ + vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG); + cmdq_src_val = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG); + + /* + * Assumption: If by any chance reset and mailbox events are reported + * together then we will only process reset event and defer the + * processing of the mailbox events. Since, we would have not cleared + * RX CMDQ event this time we would receive again another interrupt + * from H/W just for the mailbox. + */ + if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats) { /* IMP */ + val = BIT(HNS3_VECTOR0_IMPRESET_INT_B); + ret = HNS3_VECTOR0_EVENT_RST; + goto out; + } + + /* Global reset */ + if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats) { + val = BIT(HNS3_VECTOR0_GLOBALRESET_INT_B); + ret = HNS3_VECTOR0_EVENT_RST; + goto out; + } + + /* check for vector0 msix event source */ + if (vector0_int_stats & HNS3_VECTOR0_REG_MSIX_MASK) { + val = vector0_int_stats; + ret = HNS3_VECTOR0_EVENT_ERR; + goto out; + } + + /* check for vector0 mailbox(=CMDQ RX) event source */ + if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_val) { + cmdq_src_val &= ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B); + val = cmdq_src_val; + ret = HNS3_VECTOR0_EVENT_MBX; + goto out; + } + + if (clearval && (vector0_int_stats || cmdq_src_val)) + hns3_warn(hw, "surprise irq ector0_int_stats:0x%x cmdq_src_val:0x%x", + vector0_int_stats, cmdq_src_val); + val = vector0_int_stats; + ret = HNS3_VECTOR0_EVENT_OTHER; +out: + + if (clearval) + *clearval = val; + return ret; +} + +static void +hns3_clear_event_cause(struct hns3_hw *hw, uint32_t event_type, uint32_t regclr) +{ + if (event_type == HNS3_VECTOR0_EVENT_RST) + hns3_write_dev(hw, HNS3_MISC_RESET_STS_REG, regclr); + else if (event_type == HNS3_VECTOR0_EVENT_MBX) + hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr); +} + +static void +hns3_clear_all_event_cause(struct hns3_hw *hw) +{ + uint32_t vector0_int_stats; + vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG); + + if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats) + hns3_warn(hw, "Probe during IMP reset interrupt"); + + if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats) + hns3_warn(hw, "Probe during Global reset interrupt"); + + hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_RST, + BIT(HNS3_VECTOR0_IMPRESET_INT_B) | + BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) | + BIT(HNS3_VECTOR0_CORERESET_INT_B)); + hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_MBX, 0); +} + +static void +hns3_interrupt_handler(void *param) +{ + struct rte_eth_dev *dev = (struct rte_eth_dev *)param; + struct hns3_adapter *hns = dev->data->dev_private; + struct hns3_hw *hw = &hns->hw; + enum hns3_evt_cause event_cause; + uint32_t clearval = 0; + + /* Disable interrupt */ + hns3_pf_disable_irq0(hw); + + event_cause = hns3_check_event_cause(hns, &clearval); + + hns3_clear_event_cause(hw, event_cause, clearval); + /* Enable interrupt if it is not cause by reset */ + hns3_pf_enable_irq0(hw); +} + static int hns3_set_port_vlan_filter(struct hns3_adapter *hns, uint16_t vlan_id, int on) { @@ -3644,6 +3772,8 @@ hns3_init_pf(struct rte_eth_dev *eth_dev) goto err_cmd_init_queue; } + hns3_clear_all_event_cause(hw); + /* Firmware command initialize */ ret = hns3_cmd_init(hw); if (ret) { @@ -3651,6 +3781,18 @@ hns3_init_pf(struct rte_eth_dev *eth_dev) goto err_cmd_init; } + ret = rte_intr_callback_register(&pci_dev->intr_handle, + hns3_interrupt_handler, + eth_dev); + if (ret) { + PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret); + goto err_intr_callback_register; + } + + /* Enable interrupt */ + rte_intr_enable(&pci_dev->intr_handle); + hns3_pf_enable_irq0(hw); + /* Get configuration */ ret = hns3_get_configuration(hw); if (ret) { @@ -3673,12 +3815,27 @@ hns3_init_pf(struct rte_eth_dev *eth_dev) hns3_set_default_rss_args(hw); + ret = hns3_enable_hw_error_intr(hns, true); + if (ret) { + PMD_INIT_LOG(ERR, "fail to enable hw error interrupts: %d", + ret); + goto err_fdir; + } + return 0; +err_fdir: + hns3_fdir_filter_uninit(hns); err_hw_init: hns3_uninit_umv_space(hw); err_get_config: + hns3_pf_disable_irq0(hw); + rte_intr_disable(&pci_dev->intr_handle); + hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler, + eth_dev); + +err_intr_callback_register: hns3_cmd_uninit(hw); err_cmd_init: @@ -3694,13 +3851,20 @@ static void hns3_uninit_pf(struct rte_eth_dev *eth_dev) { struct hns3_adapter *hns = eth_dev->data->dev_private; + struct rte_device *dev = eth_dev->device; + struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev); struct hns3_hw *hw = &hns->hw; PMD_INIT_FUNC_TRACE(); + hns3_enable_hw_error_intr(hns, false); hns3_rss_uninit(hns); hns3_fdir_filter_uninit(hns); hns3_uninit_umv_space(hw); + hns3_pf_disable_irq0(hw); + rte_intr_disable(&pci_dev->intr_handle); + hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler, + eth_dev); hns3_cmd_uninit(hw); hns3_cmd_destroy_queue(hw); hw->io_base = NULL; diff --git a/drivers/net/hns3/hns3_ethdev_vf.c b/drivers/net/hns3/hns3_ethdev_vf.c index 64b0f11..9da42a5 100644 --- a/drivers/net/hns3/hns3_ethdev_vf.c +++ b/drivers/net/hns3/hns3_ethdev_vf.c @@ -29,6 +29,7 @@ #include "hns3_logs.h" #include "hns3_rxtx.h" #include "hns3_regs.h" +#include "hns3_intr.h" #include "hns3_dcb.h" #define HNS3VF_KEEP_ALIVE_INTERVAL 2000000 /* us */ @@ -556,6 +557,9 @@ hns3vf_interrupt_handler(void *param) enum hns3vf_evt_cause event_cause; uint32_t clearval; + if (hw->irq_thread_id == 0) + hw->irq_thread_id = pthread_self(); + /* Disable interrupt */ hns3vf_disable_irq0(hw); @@ -953,7 +957,8 @@ hns3vf_init_vf(struct rte_eth_dev *eth_dev) err_get_config: hns3vf_disable_irq0(hw); rte_intr_disable(&pci_dev->intr_handle); - + hns3_intr_unregister(&pci_dev->intr_handle, hns3vf_interrupt_handler, + eth_dev); err_intr_callback_register: hns3_cmd_uninit(hw); @@ -980,6 +985,8 @@ hns3vf_uninit_vf(struct rte_eth_dev *eth_dev) (void)hns3vf_set_promisc_mode(hw, false); hns3vf_disable_irq0(hw); rte_intr_disable(&pci_dev->intr_handle); + hns3_intr_unregister(&pci_dev->intr_handle, hns3vf_interrupt_handler, + eth_dev); hns3_cmd_uninit(hw); hns3_cmd_destroy_queue(hw); hw->io_base = NULL; diff --git a/drivers/net/hns3/hns3_intr.c b/drivers/net/hns3/hns3_intr.c new file mode 100644 index 0000000..3cf52a2 --- /dev/null +++ b/drivers/net/hns3/hns3_intr.c @@ -0,0 +1,654 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2018-2019 Hisilicon Limited. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "hns3_ethdev.h" +#include "hns3_logs.h" +#include "hns3_intr.h" +#include "hns3_regs.h" +#include "hns3_rxtx.h" + +#define SWITCH_CONTEXT_US 10 + +/* offset in MSIX bd */ +#define MAC_ERROR_OFFSET 1 +#define PPP_PF_ERROR_OFFSET 2 +#define PPU_PF_ERROR_OFFSET 3 +#define RCB_ERROR_OFFSET 5 +#define RCB_ERROR_STATUS_OFFSET 2 + +#define HNS3_CHECK_MERGE_CNT(val) \ + do { \ + if (val) \ + hw->reset.stats.merge_cnt++; \ + } while (0) + +const struct hns3_hw_error mac_afifo_tnl_int[] = { + { .int_msk = BIT(0), .msg = "egu_cge_afifo_ecc_1bit_err", + .reset_level = HNS3_NONE_RESET }, + { .int_msk = BIT(1), .msg = "egu_cge_afifo_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET }, + { .int_msk = BIT(2), .msg = "egu_lge_afifo_ecc_1bit_err", + .reset_level = HNS3_NONE_RESET }, + { .int_msk = BIT(3), .msg = "egu_lge_afifo_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET }, + { .int_msk = BIT(4), .msg = "cge_igu_afifo_ecc_1bit_err", + .reset_level = HNS3_NONE_RESET }, + { .int_msk = BIT(5), .msg = "cge_igu_afifo_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET }, + { .int_msk = BIT(6), .msg = "lge_igu_afifo_ecc_1bit_err", + .reset_level = HNS3_NONE_RESET }, + { .int_msk = BIT(7), .msg = "lge_igu_afifo_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET }, + { .int_msk = BIT(8), .msg = "cge_igu_afifo_overflow_err", + .reset_level = HNS3_GLOBAL_RESET }, + { .int_msk = BIT(9), .msg = "lge_igu_afifo_overflow_err", + .reset_level = HNS3_GLOBAL_RESET }, + { .int_msk = BIT(10), .msg = "egu_cge_afifo_underrun_err", + .reset_level = HNS3_GLOBAL_RESET }, + { .int_msk = BIT(11), .msg = "egu_lge_afifo_underrun_err", + .reset_level = HNS3_GLOBAL_RESET }, + { .int_msk = BIT(12), .msg = "egu_ge_afifo_underrun_err", + .reset_level = HNS3_GLOBAL_RESET }, + { .int_msk = BIT(13), .msg = "ge_igu_afifo_overflow_err", + .reset_level = HNS3_GLOBAL_RESET }, + { .int_msk = 0, .msg = NULL, + .reset_level = HNS3_NONE_RESET} +}; + +const struct hns3_hw_error ppu_mpf_abnormal_int_st2[] = { + { .int_msk = BIT(13), .msg = "rpu_rx_pkt_bit32_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET }, + { .int_msk = BIT(14), .msg = "rpu_rx_pkt_bit33_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET }, + { .int_msk = BIT(15), .msg = "rpu_rx_pkt_bit34_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET }, + { .int_msk = BIT(16), .msg = "rpu_rx_pkt_bit35_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET }, + { .int_msk = BIT(17), .msg = "rcb_tx_ring_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET }, + { .int_msk = BIT(18), .msg = "rcb_rx_ring_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET }, + { .int_msk = BIT(19), .msg = "rcb_tx_fbd_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET }, + { .int_msk = BIT(20), .msg = "rcb_rx_ebd_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET }, + { .int_msk = BIT(21), .msg = "rcb_tso_info_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET }, + { .int_msk = BIT(22), .msg = "rcb_tx_int_info_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET }, + { .int_msk = BIT(23), .msg = "rcb_rx_int_info_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET }, + { .int_msk = BIT(24), .msg = "tpu_tx_pkt_0_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET }, + { .int_msk = BIT(25), .msg = "tpu_tx_pkt_1_ecc_mbit_err", + .reset_level = HNS3_GLOBAL_RESET }, + { .int_msk = BIT(26), .msg = "rd_bus_err", + .reset_level = HNS3_GLOBAL_RESET }, + { .int_msk = BIT(27), .msg = "wr_bus_err", + .reset_level = HNS3_GLOBAL_RESET }, + { .int_msk = BIT(28), .msg = "reg_search_miss", + .reset_level = HNS3_GLOBAL_RESET }, + { .int_msk = BIT(29), .msg = "rx_q_search_miss", + .reset_level = HNS3_NONE_RESET }, + { .int_msk = BIT(30), .msg = "ooo_ecc_err_detect", + .reset_level = HNS3_NONE_RESET }, + { .int_msk = BIT(31), .msg = "ooo_ecc_err_multpl", + .reset_level = HNS3_GLOBAL_RESET }, + { .int_msk = 0, .msg = NULL, + .reset_level = HNS3_NONE_RESET} +}; + +const struct hns3_hw_error ssu_port_based_pf_int[] = { + { .int_msk = BIT(0), .msg = "roc_pkt_without_key_port", + .reset_level = HNS3_GLOBAL_RESET }, + { .int_msk = BIT(9), .msg = "low_water_line_err_port", + .reset_level = HNS3_NONE_RESET }, + { .int_msk = BIT(10), .msg = "hi_water_line_err_port", + .reset_level = HNS3_GLOBAL_RESET }, + { .int_msk = 0, .msg = NULL, + .reset_level = HNS3_NONE_RESET} +}; + +const struct hns3_hw_error ppp_pf_abnormal_int[] = { + { .int_msk = BIT(0), .msg = "tx_vlan_tag_err", + .reset_level = HNS3_NONE_RESET }, + { .int_msk = BIT(1), .msg = "rss_list_tc_unassigned_queue_err", + .reset_level = HNS3_NONE_RESET }, + { .int_msk = 0, .msg = NULL, + .reset_level = HNS3_NONE_RESET} +}; + +const struct hns3_hw_error ppu_pf_abnormal_int[] = { + { .int_msk = BIT(0), .msg = "over_8bd_no_fe", + .reset_level = HNS3_FUNC_RESET }, + { .int_msk = BIT(1), .msg = "tso_mss_cmp_min_err", + .reset_level = HNS3_NONE_RESET }, + { .int_msk = BIT(2), .msg = "tso_mss_cmp_max_err", + .reset_level = HNS3_NONE_RESET }, + { .int_msk = BIT(3), .msg = "tx_rd_fbd_poison", + .reset_level = HNS3_FUNC_RESET }, + { .int_msk = BIT(4), .msg = "rx_rd_ebd_poison", + .reset_level = HNS3_FUNC_RESET }, + { .int_msk = BIT(5), .msg = "buf_wait_timeout", + .reset_level = HNS3_NONE_RESET }, + { .int_msk = 0, .msg = NULL, + .reset_level = HNS3_NONE_RESET} +}; + +static int +config_ppp_err_intr(struct hns3_adapter *hns, uint32_t cmd, bool en) +{ + struct hns3_hw *hw = &hns->hw; + struct hns3_cmd_desc desc[2]; + int ret; + + /* configure PPP error interrupts */ + hns3_cmd_setup_basic_desc(&desc[0], cmd, false); + desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); + hns3_cmd_setup_basic_desc(&desc[1], cmd, false); + + if (cmd == HNS3_PPP_CMD0_INT_CMD) { + if (en) { + desc[0].data[0] = + rte_cpu_to_le_32(HNS3_PPP_MPF_ECC_ERR_INT0_EN); + desc[0].data[1] = + rte_cpu_to_le_32(HNS3_PPP_MPF_ECC_ERR_INT1_EN); + desc[0].data[4] = + rte_cpu_to_le_32(HNS3_PPP_PF_ERR_INT_EN); + } + + desc[1].data[0] = + rte_cpu_to_le_32(HNS3_PPP_MPF_ECC_ERR_INT0_EN_MASK); + desc[1].data[1] = + rte_cpu_to_le_32(HNS3_PPP_MPF_ECC_ERR_INT1_EN_MASK); + desc[1].data[2] = + rte_cpu_to_le_32(HNS3_PPP_PF_ERR_INT_EN_MASK); + } else if (cmd == HNS3_PPP_CMD1_INT_CMD) { + if (en) { + desc[0].data[0] = + rte_cpu_to_le_32(HNS3_PPP_MPF_ECC_ERR_INT2_EN); + desc[0].data[1] = + rte_cpu_to_le_32(HNS3_PPP_MPF_ECC_ERR_INT3_EN); + } + + desc[1].data[0] = + rte_cpu_to_le_32(HNS3_PPP_MPF_ECC_ERR_INT2_EN_MASK); + desc[1].data[1] = + rte_cpu_to_le_32(HNS3_PPP_MPF_ECC_ERR_INT3_EN_MASK); + } + + ret = hns3_cmd_send(hw, &desc[0], 2); + if (ret) + hns3_err(hw, "fail to configure PPP error int: %d", ret); + + return ret; +} + +static int +enable_ppp_err_intr(struct hns3_adapter *hns, bool en) +{ + int ret; + + ret = config_ppp_err_intr(hns, HNS3_PPP_CMD0_INT_CMD, en); + if (ret) + return ret; + + return config_ppp_err_intr(hns, HNS3_PPP_CMD1_INT_CMD, en); +} + +static int +enable_ssu_err_intr(struct hns3_adapter *hns, bool en) +{ + struct hns3_hw *hw = &hns->hw; + struct hns3_cmd_desc desc[2]; + int ret; + + /* configure SSU ecc error interrupts */ + hns3_cmd_setup_basic_desc(&desc[0], HNS3_SSU_ECC_INT_CMD, false); + desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); + hns3_cmd_setup_basic_desc(&desc[1], HNS3_SSU_ECC_INT_CMD, false); + if (en) { + desc[0].data[0] = + rte_cpu_to_le_32(HNS3_SSU_1BIT_ECC_ERR_INT_EN); + desc[0].data[1] = + rte_cpu_to_le_32(HNS3_SSU_MULTI_BIT_ECC_ERR_INT_EN); + desc[0].data[4] = + rte_cpu_to_le_32(HNS3_SSU_BIT32_ECC_ERR_INT_EN); + } + + desc[1].data[0] = rte_cpu_to_le_32(HNS3_SSU_1BIT_ECC_ERR_INT_EN_MASK); + desc[1].data[1] = + rte_cpu_to_le_32(HNS3_SSU_MULTI_BIT_ECC_ERR_INT_EN_MASK); + desc[1].data[2] = rte_cpu_to_le_32(HNS3_SSU_BIT32_ECC_ERR_INT_EN_MASK); + + ret = hns3_cmd_send(hw, &desc[0], 2); + if (ret) { + hns3_err(hw, "fail to configure SSU ECC error interrupt: %d", + ret); + return ret; + } + + /* configure SSU common error interrupts */ + hns3_cmd_setup_basic_desc(&desc[0], HNS3_SSU_COMMON_INT_CMD, false); + desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); + hns3_cmd_setup_basic_desc(&desc[1], HNS3_SSU_COMMON_INT_CMD, false); + + if (en) { + desc[0].data[0] = rte_cpu_to_le_32(HNS3_SSU_COMMON_INT_EN); + desc[0].data[1] = + rte_cpu_to_le_32(HNS3_SSU_PORT_BASED_ERR_INT_EN); + desc[0].data[2] = + rte_cpu_to_le_32(HNS3_SSU_FIFO_OVERFLOW_ERR_INT_EN); + } + + desc[1].data[0] = rte_cpu_to_le_32(HNS3_SSU_COMMON_INT_EN_MASK | + HNS3_SSU_PORT_BASED_ERR_INT_EN_MASK); + desc[1].data[1] = + rte_cpu_to_le_32(HNS3_SSU_FIFO_OVERFLOW_ERR_INT_EN_MASK); + + ret = hns3_cmd_send(hw, &desc[0], 2); + if (ret) + hns3_err(hw, "fail to configure SSU COMMON error intr: %d", + ret); + + return ret; +} + +static int +config_ppu_err_intrs(struct hns3_adapter *hns, uint32_t cmd, bool en) +{ + struct hns3_hw *hw = &hns->hw; + struct hns3_cmd_desc desc[2]; + int num = 1; + + /* configure PPU error interrupts */ + switch (cmd) { + case HNS3_PPU_MPF_ECC_INT_CMD: + hns3_cmd_setup_basic_desc(&desc[0], cmd, false); + desc[0].flag |= HNS3_CMD_FLAG_NEXT; + hns3_cmd_setup_basic_desc(&desc[1], cmd, false); + if (en) { + desc[0].data[0] = HNS3_PPU_MPF_ABNORMAL_INT0_EN; + desc[0].data[1] = HNS3_PPU_MPF_ABNORMAL_INT1_EN; + desc[1].data[3] = HNS3_PPU_MPF_ABNORMAL_INT3_EN; + desc[1].data[4] = HNS3_PPU_MPF_ABNORMAL_INT2_EN; + } + + desc[1].data[0] = HNS3_PPU_MPF_ABNORMAL_INT0_EN_MASK; + desc[1].data[1] = HNS3_PPU_MPF_ABNORMAL_INT1_EN_MASK; + desc[1].data[2] = HNS3_PPU_MPF_ABNORMAL_INT2_EN_MASK; + desc[1].data[3] |= HNS3_PPU_MPF_ABNORMAL_INT3_EN_MASK; + num = 2; + break; + case HNS3_PPU_MPF_OTHER_INT_CMD: + hns3_cmd_setup_basic_desc(&desc[0], cmd, false); + if (en) + desc[0].data[0] = HNS3_PPU_MPF_ABNORMAL_INT2_EN2; + + desc[0].data[2] = HNS3_PPU_MPF_ABNORMAL_INT2_EN2_MASK; + break; + case HNS3_PPU_PF_OTHER_INT_CMD: + hns3_cmd_setup_basic_desc(&desc[0], cmd, false); + if (en) + desc[0].data[0] = HNS3_PPU_PF_ABNORMAL_INT_EN; + + desc[0].data[2] = HNS3_PPU_PF_ABNORMAL_INT_EN_MASK; + break; + default: + hns3_err(hw, + "Invalid cmd(%u) to configure PPU error interrupts.", + cmd); + return -EINVAL; + } + + return hns3_cmd_send(hw, &desc[0], num); +} + +static int +enable_ppu_err_intr(struct hns3_adapter *hns, bool en) +{ + struct hns3_hw *hw = &hns->hw; + int ret; + + ret = config_ppu_err_intrs(hns, HNS3_PPU_MPF_ECC_INT_CMD, en); + if (ret) { + hns3_err(hw, "fail to configure PPU MPF ECC error intr: %d", + ret); + return ret; + } + + ret = config_ppu_err_intrs(hns, HNS3_PPU_MPF_OTHER_INT_CMD, en); + if (ret) { + hns3_err(hw, "fail to configure PPU MPF other intr: %d", + ret); + return ret; + } + + ret = config_ppu_err_intrs(hns, HNS3_PPU_PF_OTHER_INT_CMD, en); + if (ret) + hns3_err(hw, "fail to configure PPU PF error interrupts: %d", + ret); + return ret; +} + +static int +enable_mac_err_intr(struct hns3_adapter *hns, bool en) +{ + struct hns3_hw *hw = &hns->hw; + struct hns3_cmd_desc desc; + int ret; + + /* configure MAC common error interrupts */ + hns3_cmd_setup_basic_desc(&desc, HNS3_MAC_COMMON_INT_EN, false); + if (en) + desc.data[0] = rte_cpu_to_le_32(HNS3_MAC_COMMON_ERR_INT_EN); + + desc.data[1] = rte_cpu_to_le_32(HNS3_MAC_COMMON_ERR_INT_EN_MASK); + + ret = hns3_cmd_send(hw, &desc, 1); + if (ret) + hns3_err(hw, "fail to configure MAC COMMON error intr: %d", + ret); + + return ret; +} + +static const struct hns3_hw_blk hw_blk[] = { + { + .name = "PPP", + .enable_err_intr = enable_ppp_err_intr, + }, + { + .name = "SSU", + .enable_err_intr = enable_ssu_err_intr, + }, + { + .name = "PPU", + .enable_err_intr = enable_ppu_err_intr, + }, + { + .name = "MAC", + .enable_err_intr = enable_mac_err_intr, + }, + { + .name = NULL, + .enable_err_intr = NULL, + } +}; + +int +hns3_enable_hw_error_intr(struct hns3_adapter *hns, bool en) +{ + const struct hns3_hw_blk *module = hw_blk; + int ret = 0; + + while (module->enable_err_intr) { + ret = module->enable_err_intr(hns, en); + if (ret) + return ret; + + module++; + } + + return ret; +} + +static enum hns3_reset_level +hns3_find_highest_level(struct hns3_adapter *hns, const char *reg, + const struct hns3_hw_error *err, uint32_t err_sts) +{ + enum hns3_reset_level reset_level = HNS3_FUNC_RESET; + struct hns3_hw *hw = &hns->hw; + bool need_reset = false; + + while (err->msg) { + if (err->int_msk & err_sts) { + hns3_warn(hw, "%s %s found [error status=0x%x]", + reg, err->msg, err_sts); + if (err->reset_level != HNS3_NONE_RESET && + err->reset_level >= reset_level) { + reset_level = err->reset_level; + need_reset = true; + } + } + err++; + } + if (need_reset) + return reset_level; + else + return HNS3_NONE_RESET; +} + +static int +query_num_bds_in_msix(struct hns3_hw *hw, struct hns3_cmd_desc *desc_bd) +{ + int ret; + + hns3_cmd_setup_basic_desc(desc_bd, HNS3_QUERY_MSIX_INT_STS_BD_NUM, + true); + ret = hns3_cmd_send(hw, desc_bd, 1); + if (ret) + hns3_err(hw, "query num bds in msix failed: %d", ret); + + return ret; +} + +static int +query_all_mpf_msix_err(struct hns3_hw *hw, struct hns3_cmd_desc *desc, + uint32_t mpf_bd_num) +{ + int ret; + + hns3_cmd_setup_basic_desc(desc, HNS3_QUERY_CLEAR_ALL_MPF_MSIX_INT, + true); + desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); + + ret = hns3_cmd_send(hw, &desc[0], mpf_bd_num); + if (ret) + hns3_err(hw, "query all mpf msix err failed: %d", ret); + + return ret; +} + +static int +clear_all_mpf_msix_err(struct hns3_hw *hw, struct hns3_cmd_desc *desc, + uint32_t mpf_bd_num) +{ + int ret; + + hns3_cmd_reuse_desc(desc, false); + desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); + + ret = hns3_cmd_send(hw, desc, mpf_bd_num); + if (ret) + hns3_err(hw, "clear all mpf msix err failed: %d", ret); + + return ret; +} + +static int +query_all_pf_msix_err(struct hns3_hw *hw, struct hns3_cmd_desc *desc, + uint32_t pf_bd_num) +{ + int ret; + + hns3_cmd_setup_basic_desc(desc, HNS3_QUERY_CLEAR_ALL_PF_MSIX_INT, true); + desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); + + ret = hns3_cmd_send(hw, desc, pf_bd_num); + if (ret) + hns3_err(hw, "query all pf msix int cmd failed: %d", ret); + + return ret; +} + +static int +clear_all_pf_msix_err(struct hns3_hw *hw, struct hns3_cmd_desc *desc, + uint32_t pf_bd_num) +{ + int ret; + + hns3_cmd_reuse_desc(desc, false); + desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); + + ret = hns3_cmd_send(hw, desc, pf_bd_num); + if (ret) + hns3_err(hw, "clear all pf msix err failed: %d", ret); + + return ret; +} + +void +hns3_intr_unregister(const struct rte_intr_handle *hdl, + rte_intr_callback_fn cb_fn, void *cb_arg) +{ + int retry_cnt = 0; + int ret; + + do { + ret = rte_intr_callback_unregister(hdl, cb_fn, cb_arg); + if (ret >= 0) { + break; + } else if (ret != -EAGAIN) { + PMD_INIT_LOG(ERR, "Failed to unregister intr: %d", ret); + break; + } + rte_delay_ms(HNS3_INTR_UNREG_FAIL_DELAY_MS); + } while (retry_cnt++ < HNS3_INTR_UNREG_FAIL_RETRY_CNT); +} + +void +hns3_handle_msix_error(struct hns3_adapter *hns, uint64_t *levels) +{ + uint32_t mpf_bd_num, pf_bd_num, bd_num; + enum hns3_reset_level req_level; + struct hns3_hw *hw = &hns->hw; + struct hns3_pf *pf = &hns->pf; + struct hns3_cmd_desc desc_bd; + struct hns3_cmd_desc *desc; + uint32_t *desc_data; + uint32_t status; + int ret; + + /* query the number of bds for the MSIx int status */ + ret = query_num_bds_in_msix(hw, &desc_bd); + if (ret) { + hns3_err(hw, "fail to query msix int status bd num: %d", ret); + return; + } + + mpf_bd_num = rte_le_to_cpu_32(desc_bd.data[0]); + pf_bd_num = rte_le_to_cpu_32(desc_bd.data[1]); + bd_num = max_t(uint32_t, mpf_bd_num, pf_bd_num); + if (bd_num < RCB_ERROR_OFFSET) { + hns3_err(hw, "bd_num is less than RCB_ERROR_OFFSET: %u", + bd_num); + return; + } + + desc = rte_zmalloc(NULL, bd_num * sizeof(struct hns3_cmd_desc), 0); + if (desc == NULL) { + hns3_err(hw, "fail to zmalloc desc"); + return; + } + + /* query all main PF MSIx errors */ + ret = query_all_mpf_msix_err(hw, &desc[0], mpf_bd_num); + if (ret) { + hns3_err(hw, "query all mpf msix int cmd failed: %d", ret); + goto out; + } + + /* log MAC errors */ + desc_data = (uint32_t *)&desc[MAC_ERROR_OFFSET]; + status = rte_le_to_cpu_32(*desc_data); + if (status) { + req_level = hns3_find_highest_level(hns, "MAC_AFIFO_TNL_INT_R", + mac_afifo_tnl_int, + status); + hns3_atomic_set_bit(req_level, levels); + pf->abn_int_stats.mac_afifo_tnl_intr_cnt++; + } + + /* log PPU(RCB) errors */ + desc_data = (uint32_t *)&desc[RCB_ERROR_OFFSET]; + status = rte_le_to_cpu_32(*(desc_data + RCB_ERROR_STATUS_OFFSET)) & + HNS3_PPU_MPF_INT_ST2_MSIX_MASK; + if (status) { + req_level = hns3_find_highest_level(hns, + "PPU_MPF_ABNORMAL_INT_ST2", + ppu_mpf_abnormal_int_st2, + status); + hns3_atomic_set_bit(req_level, levels); + pf->abn_int_stats.ppu_mpf_abnormal_intr_st2_cnt++; + } + + /* clear all main PF MSIx errors */ + ret = clear_all_mpf_msix_err(hw, desc, mpf_bd_num); + if (ret) { + hns3_err(hw, "clear all mpf msix int cmd failed: %d", ret); + goto out; + } + + /* query all PF MSIx errors */ + memset(desc, 0, bd_num * sizeof(struct hns3_cmd_desc)); + ret = query_all_pf_msix_err(hw, &desc[0], pf_bd_num); + if (ret) { + hns3_err(hw, "query all pf msix int cmd failed (%d)", ret); + goto out; + } + + /* log SSU PF errors */ + status = rte_le_to_cpu_32(desc[0].data[0]) & + HNS3_SSU_PORT_INT_MSIX_MASK; + if (status) { + req_level = hns3_find_highest_level(hns, + "SSU_PORT_BASED_ERR_INT", + ssu_port_based_pf_int, + status); + hns3_atomic_set_bit(req_level, levels); + pf->abn_int_stats.ssu_port_based_pf_intr_cnt++; + } + + /* log PPP PF errors */ + desc_data = (uint32_t *)&desc[PPP_PF_ERROR_OFFSET]; + status = rte_le_to_cpu_32(*desc_data); + if (status) { + req_level = hns3_find_highest_level(hns, + "PPP_PF_ABNORMAL_INT_ST0", + ppp_pf_abnormal_int, + status); + hns3_atomic_set_bit(req_level, levels); + pf->abn_int_stats.ppp_pf_abnormal_intr_cnt++; + } + + /* log PPU(RCB) PF errors */ + desc_data = (uint32_t *)&desc[PPU_PF_ERROR_OFFSET]; + status = rte_le_to_cpu_32(*desc_data) & HNS3_PPU_PF_INT_MSIX_MASK; + if (status) { + req_level = hns3_find_highest_level(hns, + "PPU_PF_ABNORMAL_INT_ST", + ppu_pf_abnormal_int, + status); + hns3_atomic_set_bit(req_level, levels); + pf->abn_int_stats.ppu_pf_abnormal_intr_cnt++; + } + + /* clear all PF MSIx errors */ + ret = clear_all_pf_msix_err(hw, desc, pf_bd_num); + if (ret) + hns3_err(hw, "clear all pf msix int cmd failed: %d", ret); +out: + rte_free(desc); +} diff --git a/drivers/net/hns3/hns3_intr.h b/drivers/net/hns3/hns3_intr.h new file mode 100644 index 0000000..b57b4ac --- /dev/null +++ b/drivers/net/hns3/hns3_intr.h @@ -0,0 +1,68 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2018-2019 Hisilicon Limited. + */ + +#ifndef _HNS3_INTR_H_ +#define _HNS3_INTR_H_ + +#define HNS3_PPP_MPF_ECC_ERR_INT0_EN 0xFFFFFFFF +#define HNS3_PPP_MPF_ECC_ERR_INT0_EN_MASK 0xFFFFFFFF +#define HNS3_PPP_MPF_ECC_ERR_INT1_EN 0xFFFFFFFF +#define HNS3_PPP_MPF_ECC_ERR_INT1_EN_MASK 0xFFFFFFFF +#define HNS3_PPP_PF_ERR_INT_EN 0x0003 +#define HNS3_PPP_PF_ERR_INT_EN_MASK 0x0003 +#define HNS3_PPP_MPF_ECC_ERR_INT2_EN 0x003F +#define HNS3_PPP_MPF_ECC_ERR_INT2_EN_MASK 0x003F +#define HNS3_PPP_MPF_ECC_ERR_INT3_EN 0x003F +#define HNS3_PPP_MPF_ECC_ERR_INT3_EN_MASK 0x003F + +#define HNS3_MAC_COMMON_ERR_INT_EN 0x107FF +#define HNS3_MAC_COMMON_ERR_INT_EN_MASK 0x107FF + +#define HNS3_PPU_MPF_ABNORMAL_INT0_EN GENMASK(31, 0) +#define HNS3_PPU_MPF_ABNORMAL_INT0_EN_MASK GENMASK(31, 0) +#define HNS3_PPU_MPF_ABNORMAL_INT1_EN GENMASK(31, 0) +#define HNS3_PPU_MPF_ABNORMAL_INT1_EN_MASK GENMASK(31, 0) +#define HNS3_PPU_MPF_ABNORMAL_INT2_EN 0x3FFF3FFF +#define HNS3_PPU_MPF_ABNORMAL_INT2_EN_MASK 0x3FFF3FFF +#define HNS3_PPU_MPF_ABNORMAL_INT2_EN2 0xB +#define HNS3_PPU_MPF_ABNORMAL_INT2_EN2_MASK 0xB +#define HNS3_PPU_MPF_ABNORMAL_INT3_EN GENMASK(7, 0) +#define HNS3_PPU_MPF_ABNORMAL_INT3_EN_MASK GENMASK(23, 16) +#define HNS3_PPU_PF_ABNORMAL_INT_EN GENMASK(5, 0) +#define HNS3_PPU_PF_ABNORMAL_INT_EN_MASK GENMASK(5, 0) +#define HNS3_PPU_PF_INT_MSIX_MASK 0x27 +#define HNS3_PPU_MPF_INT_ST2_MSIX_MASK GENMASK(29, 28) + +#define HNS3_SSU_1BIT_ECC_ERR_INT_EN GENMASK(31, 0) +#define HNS3_SSU_1BIT_ECC_ERR_INT_EN_MASK GENMASK(31, 0) +#define HNS3_SSU_MULTI_BIT_ECC_ERR_INT_EN GENMASK(31, 0) +#define HNS3_SSU_MULTI_BIT_ECC_ERR_INT_EN_MASK GENMASK(31, 0) +#define HNS3_SSU_BIT32_ECC_ERR_INT_EN 0x0101 +#define HNS3_SSU_BIT32_ECC_ERR_INT_EN_MASK 0x0101 +#define HNS3_SSU_COMMON_INT_EN GENMASK(9, 0) +#define HNS3_SSU_COMMON_INT_EN_MASK GENMASK(9, 0) +#define HNS3_SSU_PORT_BASED_ERR_INT_EN 0x0BFF +#define HNS3_SSU_PORT_BASED_ERR_INT_EN_MASK 0x0BFF0000 +#define HNS3_SSU_FIFO_OVERFLOW_ERR_INT_EN GENMASK(23, 0) +#define HNS3_SSU_FIFO_OVERFLOW_ERR_INT_EN_MASK GENMASK(23, 0) +#define HNS3_SSU_COMMON_ERR_INT_MASK GENMASK(9, 0) +#define HNS3_SSU_PORT_INT_MSIX_MASK 0x7BFF + +struct hns3_hw_blk { + const char *name; + int (*enable_err_intr)(struct hns3_adapter *hns, bool en); +}; + +struct hns3_hw_error { + uint32_t int_msk; + const char *msg; + enum hns3_reset_level reset_level; +}; + +int hns3_enable_hw_error_intr(struct hns3_adapter *hns, bool state); +void hns3_handle_msix_error(struct hns3_adapter *hns, uint64_t *levels); +void hns3_intr_unregister(const struct rte_intr_handle *hdl, + rte_intr_callback_fn cb_fn, void *cb_arg); + +#endif /* _HNS3_INTR_H_ */ diff --git a/drivers/net/hns3/hns3_mbx.c b/drivers/net/hns3/hns3_mbx.c index 200eb77..c03e71d 100644 --- a/drivers/net/hns3/hns3_mbx.c +++ b/drivers/net/hns3/hns3_mbx.c @@ -22,6 +22,7 @@ #include "hns3_ethdev.h" #include "hns3_regs.h" #include "hns3_logs.h" +#include "hns3_intr.h" #define HNS3_REG_MSG_DATA_OFFSET 4 #define HNS3_CMD_CODE_OFFSET 2 diff --git a/drivers/net/hns3/meson.build b/drivers/net/hns3/meson.build index 77d9154..519af97 100644 --- a/drivers/net/hns3/meson.build +++ b/drivers/net/hns3/meson.build @@ -15,6 +15,7 @@ endif sources = files('hns3_cmd.c', 'hns3_dcb.c', + 'hns3_intr.c', 'hns3_ethdev.c', 'hns3_ethdev_vf.c', 'hns3_fdir.c',