From: Qiming Yang <qiming.yang@intel.com>
Added a devarg to control the mode in generic flow API.
We use none-pipeline mode by default.
Signed-off-by: Qiming Yang <qiming.yang@intel.com>
---
doc/guides/nics/ice.rst | 19 +++++++++++++++++++
doc/guides/rel_notes/release_19_11.rst | 2 ++
drivers/net/ice/ice_ethdev.c | 11 ++++++++++-
drivers/net/ice/ice_ethdev.h | 1 +
4 files changed, 32 insertions(+), 1 deletion(-)
@@ -61,6 +61,25 @@ Runtime Config Options
NOTE: In Safe mode, only very limited features are available, features like RSS,
checksum, fdir, tunneling ... are all disabled.
+- ``Generic Flow Pipeline Mode Support`` (default ``0``)
+
+ In pipeline mode, a flow can be set at one specific stage by setting parameter
+ ``priority``. Currently, we support two stages: priority = 0 or !0. Flows with
+ priority 0 located at the first pipeline stage which typically be used as a firewall
+ to drop the packet on a blacklist(we called it permission stage). At this stage,
+ flow rules are created for the device's exact match engine: switch. Flows with priority
+ !0 located at the second stage, typically packets are classified here and be steered to
+ specific queue or queue group (we called it distribution stage), At this stage, flow
+ rules are created for device's flow director engine.
+ For none-pipeline mode, ``priority`` is ignored, a flow rule can be created as a flow director
+ rule or a switch rule depends on its pattern/action and the resource allocation situation,
+ all flows are virtually at the same pipeline stage.
+ By default, generic flow API is enabled in none-pipeline mode, user can choose to
+ use pipeline mode by setting ``devargs`` parameter ``pipeline-mode-support``,
+ for example::
+
+ -w 80:00.0,pipleline-mode-support=1
+
Driver compilation and testing
------------------------------
@@ -61,6 +61,8 @@ New Features
Updated the Intel ice driver with new features and improvements, including:
* Supported device-specific DDP package loading.
+ * Generic filter enhancement
+ - Supported pipeline mode.
Removed Items
-------------
@@ -19,9 +19,11 @@
/* devargs */
#define ICE_SAFE_MODE_SUPPORT_ARG "safe-mode-support"
+#define ICE_PIPELINE_MODE_SUPPORT_ARG "pipeline-mode-support"
static const char * const ice_valid_args[] = {
ICE_SAFE_MODE_SUPPORT_ARG,
+ ICE_PIPELINE_MODE_SUPPORT_ARG,
NULL
};
@@ -1510,7 +1512,13 @@ static int ice_parse_devargs(struct rte_eth_dev *dev)
ret = rte_kvargs_process(kvlist, ICE_SAFE_MODE_SUPPORT_ARG,
&parse_bool, &ad->devargs.safe_mode_support);
+ if (ret)
+ goto err_devargs;
+
+ ret = rte_kvargs_process(kvlist, ICE_PIPELINE_MODE_SUPPORT_ARG,
+ &parse_bool, &ad->devargs.pipeline_mode_support);
+err_devargs:
rte_kvargs_free(kvlist);
return ret;
}
@@ -3925,7 +3933,8 @@ RTE_PMD_REGISTER_PCI(net_ice, rte_ice_pmd);
RTE_PMD_REGISTER_PCI_TABLE(net_ice, pci_id_ice_map);
RTE_PMD_REGISTER_KMOD_DEP(net_ice, "* igb_uio | uio_pci_generic | vfio-pci");
RTE_PMD_REGISTER_PARAM_STRING(net_ice,
- ICE_SAFE_MODE_SUPPORT_ARG "=<0|1>");
+ ICE_SAFE_MODE_SUPPORT_ARG "=<0|1>"
+ ICE_PIPELINE_MODE_SUPPORT_ARG "=<0|1>");
RTE_INIT(ice_init_log)
{
@@ -285,6 +285,7 @@ struct ice_pf {
*/
struct ice_devargs {
int safe_mode_support;
+ int pipeline_mode_support;
};
/**