From patchwork Fri Aug 30 20:51:56 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lance Richardson X-Patchwork-Id: 58322 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 9A5391EA32; Fri, 30 Aug 2019 22:53:00 +0200 (CEST) Received: from mail-pl1-f195.google.com (mail-pl1-f195.google.com [209.85.214.195]) by dpdk.org (Postfix) with ESMTP id 667A31EA12 for ; Fri, 30 Aug 2019 22:52:57 +0200 (CEST) Received: by mail-pl1-f195.google.com with SMTP id y1so3864778plp.9 for ; Fri, 30 Aug 2019 13:52:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=mEZra6BKOEftucTKH/9qwR2k3AgZvIutfGcnT1HLWl0=; b=CpOZAnCd8mAWfAKJD/qZuybIJfEHnFb55KY2bW8VlkITSzFyd3srld5QM383N5zAjM ZSHTWCdmPozoNMsEVpUgqVd2wbFQrrINHxZXd4u5XSc09OoDok5N6/e6LWLKoghmwB4D 4ZtQ+z+U1SMImg8ka1qTZJOnngahV6RQ3/GPA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=mEZra6BKOEftucTKH/9qwR2k3AgZvIutfGcnT1HLWl0=; b=qfB6XG4E+b05WrWuNwxB1VsQ8Ja7DCH8ZqKb96VagckrD9XT0SILHSyhawpPsjWKh8 MZCLK76DJ4fdTHhLsb+32M8WUsur8i/dzZrDnk45xLUYYadTBkT9x92FcpmQHUPNLlWA Zr/sfoTJVWLPe3eK5n9CnJl3HonEF96CjhkKt9l6WUDQUIdaL0MEJFmvj2Eo8kRHNWpn okbgq2bTcNHfRCgk81XDal4Wxv5DnrKVYoSl098WIN3koTGGHmIIY1E5irrAlCqs4MaK 3yT1mcMsN+Q6m3pr0Ukjx54gPx1+lSRiw8sINdSeQi1lk0OHmTH5iIvmnlJNJTJ9+o4l mgfw== X-Gm-Message-State: APjAAAXL8lhLgwsw8MLiUupigb70m0aSzEa2DVDk+qJHsjhAM/zhe6HG 8WwphLmke6iHJiwwUqdR9Kz9zcvYhxfX3AHEXrKa6lLbpvnJviFHiz3dqGSBVTOK/J153OZnCKN PRTGXUS9S9kSko0w275bI24iNvccramwcN39jWDiuW/POZaRqrjzoF2uxkf6l8lq/ X-Google-Smtp-Source: APXvYqzrvVGGSE8p5V4nqiXqrrniEaI7FAGguM4sM4AziAmjpmMW8iUvxlLLhvR90F/d6HRGOjA5vg== X-Received: by 2002:a17:902:524:: with SMTP id 33mr17912731plf.27.1567198376504; Fri, 30 Aug 2019 13:52:56 -0700 (PDT) Received: from localhost.localdomain ([192.19.231.250]) by smtp.gmail.com with ESMTPSA id i14sm3761369pfo.158.2019.08.30.13.52.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Aug 2019 13:52:56 -0700 (PDT) From: Lance Richardson To: dev@dpdk.org Cc: ajit.khaparde@broadcom.com, ferruh.yigit@intel.com, Lance Richardson Date: Fri, 30 Aug 2019 16:51:56 -0400 Message-Id: <20190830205201.26644-3-lance.richardson@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190830205201.26644-1-lance.richardson@broadcom.com> References: <20190830205201.26644-1-lance.richardson@broadcom.com> Subject: [dpdk-dev] [PATCH 2/7] net/bnxt: fix ring alignment for thor-based adapters X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" When using transmit/receive queue sizes smaller than 256, alignment requirements are not being met for Thor-based adapters. Fix by forcing memory addresses used for transmit/receive/aggregation ring allocations to be on 4K boundaries. Fixes: f8168ca0e690 ("net/bnxt: support thor controller") Signed-off-by: Lance Richardson Reviewed-by: Ajit Kumar Khaparde --- drivers/net/bnxt/bnxt_ring.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/net/bnxt/bnxt_ring.c b/drivers/net/bnxt/bnxt_ring.c index ec17783cf..bc8b92b04 100644 --- a/drivers/net/bnxt/bnxt_ring.c +++ b/drivers/net/bnxt/bnxt_ring.c @@ -162,18 +162,21 @@ int bnxt_alloc_rings(struct bnxt *bp, uint16_t qidx, int nq_ring_len = BNXT_CHIP_THOR(bp) ? cp_ring_len : 0; int tx_ring_start = nq_ring_start + nq_ring_len; + tx_ring_start = RTE_ALIGN(tx_ring_start, 4096); int tx_ring_len = tx_ring_info ? RTE_CACHE_LINE_ROUNDUP(tx_ring_info->tx_ring_struct->ring_size * sizeof(struct tx_bd_long)) : 0; tx_ring_len = RTE_ALIGN(tx_ring_len, 4096); int rx_ring_start = tx_ring_start + tx_ring_len; + rx_ring_start = RTE_ALIGN(rx_ring_start, 4096); int rx_ring_len = rx_ring_info ? RTE_CACHE_LINE_ROUNDUP(rx_ring_info->rx_ring_struct->ring_size * sizeof(struct rx_prod_pkt_bd)) : 0; rx_ring_len = RTE_ALIGN(rx_ring_len, 4096); int ag_ring_start = rx_ring_start + rx_ring_len; + ag_ring_start = RTE_ALIGN(ag_ring_start, 4096); int ag_ring_len = rx_ring_len * AGG_RING_SIZE_FACTOR; ag_ring_len = RTE_ALIGN(ag_ring_len, 4096);