From patchwork Fri Aug 23 13:46:56 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Wei Hu (Xavier)" X-Patchwork-Id: 57849 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id B821D1BFF6; Fri, 23 Aug 2019 15:49:55 +0200 (CEST) Received: from huawei.com (szxga07-in.huawei.com [45.249.212.35]) by dpdk.org (Postfix) with ESMTP id BDF4A1BFCB for ; Fri, 23 Aug 2019 15:49:37 +0200 (CEST) Received: from DGGEMS406-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id B6E029EBF6F3812BFAB6; Fri, 23 Aug 2019 21:49:36 +0800 (CST) Received: from localhost.localdomain (10.67.212.132) by DGGEMS406-HUB.china.huawei.com (10.3.19.206) with Microsoft SMTP Server id 14.3.439.0; Fri, 23 Aug 2019 21:49:27 +0800 From: "Wei Hu (Xavier)" To: CC: , , , Date: Fri, 23 Aug 2019 21:46:56 +0800 Message-ID: <1566568031-45991-8-git-send-email-xavier.huwei@huawei.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1566568031-45991-1-git-send-email-xavier.huwei@huawei.com> References: <1566568031-45991-1-git-send-email-xavier.huwei@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.132] X-CFilter-Loop: Reflected Subject: [dpdk-dev] [PATCH 07/22] net/hns3: add support for some misc operations X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This patch adds the following operations defined in struct eth_dev_ops: mtu_set, infos_get and fw_version_get for hns3 PMD driver. Signed-off-by: Wei Hu (Xavier) Signed-off-by: Chunsong Feng Signed-off-by: Min Hu (Connor) Signed-off-by: Hao Chen Signed-off-by: Huisong Li --- drivers/net/hns3/hns3_ethdev.c | 137 ++++++++++++++++++++++++++++++++++++++++- 1 file changed, 136 insertions(+), 1 deletion(-) diff --git a/drivers/net/hns3/hns3_ethdev.c b/drivers/net/hns3/hns3_ethdev.c index 44e21ac..ced9348 100644 --- a/drivers/net/hns3/hns3_ethdev.c +++ b/drivers/net/hns3/hns3_ethdev.c @@ -40,6 +40,8 @@ int hns3_logtype_init; int hns3_logtype_driver; +static int hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu); + static int hns3_config_tso(struct hns3_hw *hw, unsigned int tso_mss_min, unsigned int tso_mss_max) @@ -1000,6 +1002,131 @@ hns3_config_mtu(struct hns3_hw *hw, uint16_t mps) } static int +hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) +{ + struct hns3_adapter *hns = dev->data->dev_private; + uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD; + struct hns3_hw *hw = &hns->hw; + bool is_jumbo_frame; + int ret; + + if (mtu < RTE_ETHER_MIN_MTU || frame_size > HNS3_MAX_FRAME_LEN) { + hns3_err(hw, "Failed to set mtu, mtu(%u) invalid. valid " + "range: %d~%d", mtu, RTE_ETHER_MIN_MTU, HNS3_MAX_MTU); + return -EINVAL; + } + + if (dev->data->dev_started) { + hns3_err(hw, "Failed to set mtu, port %u must be stopped " + "before configuration", dev->data->port_id); + return -EBUSY; + } + + rte_spinlock_lock(&hw->lock); + is_jumbo_frame = frame_size > RTE_ETHER_MAX_LEN ? true : false; + frame_size = RTE_MAX(frame_size, HNS3_DEFAULT_FRAME_LEN); + + /* + * Maximum value of frame_size is HNS3_MAX_FRAME_LEN, so it can safely + * assign to "uint16_t" type variable. + */ + ret = hns3_config_mtu(hw, (uint16_t)frame_size); + if (ret) { + rte_spinlock_unlock(&hw->lock); + hns3_err(hw, "Failed to set mtu, port %u mtu %u: %d", + dev->data->port_id, mtu, ret); + return ret; + } + hns->pf.mps = (uint16_t)frame_size; + if (is_jumbo_frame) + dev->data->dev_conf.rxmode.offloads |= + DEV_RX_OFFLOAD_JUMBO_FRAME; + else + dev->data->dev_conf.rxmode.offloads &= + ~DEV_RX_OFFLOAD_JUMBO_FRAME; + dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size; + rte_spinlock_unlock(&hw->lock); + + return 0; +} + +static void +hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info) +{ + struct hns3_adapter *hns = eth_dev->data->dev_private; + struct hns3_hw *hw = &hns->hw; + + info->max_rx_queues = hw->tqps_num; + info->max_tx_queues = hw->tqps_num; + info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */ + info->min_rx_bufsize = hw->rx_buf_len; + info->max_mac_addrs = HNS3_UC_MACADDR_NUM; + info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD; + info->min_mtu = RTE_ETHER_MIN_MTU; + info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM | + DEV_RX_OFFLOAD_UDP_CKSUM | + DEV_RX_OFFLOAD_TCP_CKSUM | + DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | + DEV_RX_OFFLOAD_OUTER_UDP_CKSUM | + DEV_RX_OFFLOAD_KEEP_CRC | + DEV_RX_OFFLOAD_SCATTER | + DEV_RX_OFFLOAD_VLAN_STRIP | + DEV_RX_OFFLOAD_QINQ_STRIP | + DEV_RX_OFFLOAD_VLAN_FILTER | + DEV_RX_OFFLOAD_VLAN_EXTEND | + DEV_RX_OFFLOAD_JUMBO_FRAME); + info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE; + info->tx_offload_capa = (DEV_TX_OFFLOAD_IPV4_CKSUM | + DEV_TX_OFFLOAD_UDP_CKSUM | + DEV_TX_OFFLOAD_TCP_CKSUM | + DEV_TX_OFFLOAD_VLAN_INSERT | + DEV_TX_OFFLOAD_QINQ_INSERT | + DEV_TX_OFFLOAD_MULTI_SEGS | + info->tx_queue_offload_capa); + + info->rx_desc_lim = (struct rte_eth_desc_lim) { + .nb_max = HNS3_MAX_RING_DESC, + .nb_min = HNS3_MIN_RING_DESC, + .nb_align = HNS3_ALIGN_RING_DESC, + }; + + info->tx_desc_lim = (struct rte_eth_desc_lim) { + .nb_max = HNS3_MAX_RING_DESC, + .nb_min = HNS3_MIN_RING_DESC, + .nb_align = HNS3_ALIGN_RING_DESC, + }; + + info->vmdq_queue_num = 0; + + info->reta_size = HNS3_RSS_IND_TBL_SIZE; + info->hash_key_size = HNS3_RSS_KEY_SIZE; + info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT; + + info->default_rxportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE; + info->default_txportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE; + info->default_rxportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM; + info->default_txportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM; + info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC; + info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC; +} + +static int +hns3_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version, + size_t fw_size) +{ + struct hns3_adapter *hns = eth_dev->data->dev_private; + struct hns3_hw *hw = &hns->hw; + int ret; + + ret = snprintf(fw_version, fw_size, "0x%08x", hw->fw_version); + ret += 1; /* add the size of '\0' */ + if (fw_size < (uint32_t)ret) + return ret; + else + return 0; +} + +static int hns3_parse_func_status(struct hns3_hw *hw, struct hns3_func_status_cmd *status) { struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); @@ -2394,6 +2521,9 @@ hns3_dev_close(struct rte_eth_dev *eth_dev) static const struct eth_dev_ops hns3_eth_dev_ops = { .dev_close = hns3_dev_close, + .mtu_set = hns3_dev_mtu_set, + .dev_infos_get = hns3_dev_infos_get, + .fw_version_get = hns3_fw_version_get, .mac_addr_add = hns3_add_mac_addr, .mac_addr_remove = hns3_remove_mac_addr, .mac_addr_set = hns3_set_default_mac_addr, @@ -2420,7 +2550,12 @@ hns3_dev_init(struct rte_eth_dev *eth_dev) hns->is_vf = false; hw->data = eth_dev->data; - hns->pf.mps = HNS3_DEFAULT_FRAME_LEN; + + /* + * Set default max packet size according to the mtu + * default vale in DPDK frame. + */ + hns->pf.mps = hw->data->mtu + HNS3_ETH_OVERHEAD; ret = hns3_init_pf(eth_dev); if (ret) {