From patchwork Fri Jun 28 07:50:21 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pavan Nikhilesh Bhagavatula X-Patchwork-Id: 55577 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 0EC271BB6F; Fri, 28 Jun 2019 09:52:58 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by dpdk.org (Postfix) with ESMTP id 7BBE51B9AA for ; Fri, 28 Jun 2019 09:51:57 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x5S7ofnx025743 for ; Fri, 28 Jun 2019 00:51:56 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0818; bh=a06FMPRrs5rQ09iAlIbcdZgd9UKrcpDt4G7UyMPRQYI=; b=DzmEWAnkiq91vB11AaXp3NqmxaSqxh6EiWz9rD7h3hf04BaDX7E/7xNmnvysXj/mkAKk mGWFhMXFwQ9WBr3XngB6cNNckP7a0ZYrpALt74+F6AMSkPbFrj4xJ9WXT273oeL47zQO QvEoKkZh//0/WCUO9DH3xuqWLNRd/JyQ6iN3Tsf/E8ZCgI+8Ls5OdU24Lr4sfbZrWky1 nzKVU93emOGWMV3psMUSjqwT1fEI9H5Tq0r22HFwMXC3nyjfxcBNRqX0inA+ZzRzNdNS yYSPZR7EPDxaDfN3OfAkkjKEpqAzpacI5tgivUTFazFip+4nfyfC4mQBHAXODueT0B8E 5Q== Received: from sc-exch04.marvell.com ([199.233.58.184]) by mx0b-0016f401.pphosted.com with ESMTP id 2tcvnhc6mg-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Fri, 28 Jun 2019 00:51:56 -0700 Received: from SC-EXCH01.marvell.com (10.93.176.81) by SC-EXCH04.marvell.com (10.93.176.84) with Microsoft SMTP Server (TLS) id 15.0.1367.3; Fri, 28 Jun 2019 00:51:55 -0700 Received: from maili.marvell.com (10.93.176.43) by SC-EXCH01.marvell.com (10.93.176.81) with Microsoft SMTP Server id 15.0.1367.3 via Frontend Transport; Fri, 28 Jun 2019 00:51:54 -0700 Received: from BG-LT7430.marvell.com (bg-lt7430.marvell.com [10.28.10.255]) by maili.marvell.com (Postfix) with ESMTP id D84233F7040; Fri, 28 Jun 2019 00:51:53 -0700 (PDT) From: To: CC: , Pavan Nikhilesh Date: Fri, 28 Jun 2019 13:20:21 +0530 Message-ID: <20190628075024.404-43-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190628075024.404-1-pbhagavatula@marvell.com> References: <20190628075024.404-1-pbhagavatula@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-06-28_02:, , signatures=0 Subject: [dpdk-dev] [PATCH v2 42/44] event/octeontx2: add devargs to limit timer adapters X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Pavan Nikhilesh Add devargs to limit the max number of TIM rings reserved on probe. Since, TIM rings are HW resources we can avoid starving other applications by not grabbing all the rings. Example: --dev "0002:0e:00.0,tim_rings_lmt=2" Signed-off-by: Pavan Nikhilesh --- drivers/event/octeontx2/otx2_tim_evdev.c | 6 +++++- drivers/event/octeontx2/otx2_tim_evdev.h | 1 + 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/event/octeontx2/otx2_tim_evdev.c b/drivers/event/octeontx2/otx2_tim_evdev.c index cd9a679fb..c312bd541 100644 --- a/drivers/event/octeontx2/otx2_tim_evdev.c +++ b/drivers/event/octeontx2/otx2_tim_evdev.c @@ -527,6 +527,7 @@ otx2_tim_caps_get(const struct rte_eventdev *evdev, uint64_t flags, #define OTX2_TIM_DISABLE_NPA "tim_disable_npa" #define OTX2_TIM_CHNK_SLOTS "tim_chnk_slots" #define OTX2_TIM_STATS_ENA "tim_stats_ena" +#define OTX2_TIM_RINGS_LMT "tim_rings_lmt" static void tim_parse_devargs(struct rte_devargs *devargs, struct otx2_tim_evdev *dev) @@ -546,6 +547,8 @@ tim_parse_devargs(struct rte_devargs *devargs, struct otx2_tim_evdev *dev) &parse_kvargs_value, &dev->chunk_slots); rte_kvargs_process(kvlist, OTX2_TIM_STATS_ENA, &parse_kvargs_flag, &dev->enable_stats); + rte_kvargs_process(kvlist, OTX2_TIM_RINGS_LMT, &parse_kvargs_value, + &dev->min_ring_cnt); } void @@ -583,7 +586,8 @@ otx2_tim_init(struct rte_pci_device *pci_dev, struct otx2_dev *cmn_dev) goto mz_free; } - dev->nb_rings = rsrc_cnt->tim; + dev->nb_rings = dev->min_ring_cnt ? + RTE_MIN(dev->min_ring_cnt, rsrc_cnt->tim) : rsrc_cnt->tim; if (!dev->nb_rings) { otx2_tim_dbg("No TIM Logical functions provisioned."); diff --git a/drivers/event/octeontx2/otx2_tim_evdev.h b/drivers/event/octeontx2/otx2_tim_evdev.h index c8d16b03f..5af724ef9 100644 --- a/drivers/event/octeontx2/otx2_tim_evdev.h +++ b/drivers/event/octeontx2/otx2_tim_evdev.h @@ -121,6 +121,7 @@ struct otx2_tim_evdev { /* Dev args */ uint8_t disable_npa; uint16_t chunk_slots; + uint16_t min_ring_cnt; uint8_t enable_stats; /* MSIX offsets */ uint16_t tim_msixoff[OTX2_MAX_TIM_RINGS];