[v2,21/66] net/ice/base: add helper functions for PHY caching
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Commit Message
Add additional functions to aide in caching PHY configuration.
In order to cache the initial modes, we need to determine the
operating mode based on capabilities. Add helper functions
for flow control and FEC to take a set of capabilities and
return the operating mode matching those capabilities. Also
add a helper function to determine whether a PHY capability
matches a PHY configuration.
Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Leyi Rong <leyi.rong@intel.com>
---
drivers/net/ice/base/ice_adminq_cmd.h | 1 +
drivers/net/ice/base/ice_common.c | 83 +++++++++++++++++++++++++++
drivers/net/ice/base/ice_common.h | 9 ++-
3 files changed, 91 insertions(+), 2 deletions(-)
Comments
> -----Original Message-----
> From: Rong, Leyi
> Sent: Tuesday, June 11, 2019 8:52 AM
> To: Zhang, Qi Z <qi.z.zhang@intel.com>
> Cc: dev@dpdk.org; Rong, Leyi <leyi.rong@intel.com>; Nguyen, Anthony L
> <anthony.l.nguyen@intel.com>; Stillwell Jr, Paul M
> <paul.m.stillwell.jr@intel.com>
> Subject: [PATCH v2 21/66] net/ice/base: add helper functions for PHY caching
>
> Add additional functions to aide in caching PHY configuration.
> In order to cache the initial modes, we need to determine the operating
> mode based on capabilities. Add helper functions for flow control and FEC to
> take a set of capabilities and return the operating mode matching those
> capabilities. Also add a helper function to determine whether a PHY capability
> matches a PHY configuration.
>
> Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
> Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
> Signed-off-by: Leyi Rong <leyi.rong@intel.com>
> ---
> drivers/net/ice/base/ice_adminq_cmd.h | 1 +
> drivers/net/ice/base/ice_common.c | 83
> +++++++++++++++++++++++++++
> drivers/net/ice/base/ice_common.h | 9 ++-
> 3 files changed, 91 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/net/ice/base/ice_adminq_cmd.h
> b/drivers/net/ice/base/ice_adminq_cmd.h
> index 739f79e88..77f93b950 100644
> --- a/drivers/net/ice/base/ice_adminq_cmd.h
> +++ b/drivers/net/ice/base/ice_adminq_cmd.h
> @@ -1594,6 +1594,7 @@ struct ice_aqc_get_link_status_data {
> #define ICE_AQ_LINK_PWR_QSFP_CLASS_3 2
> #define ICE_AQ_LINK_PWR_QSFP_CLASS_4 3
> __le16 link_speed;
> +#define ICE_AQ_LINK_SPEED_M 0x7FF
> #define ICE_AQ_LINK_SPEED_10MB BIT(0)
> #define ICE_AQ_LINK_SPEED_100MB BIT(1)
> #define ICE_AQ_LINK_SPEED_1000MB BIT(2)
> diff --git a/drivers/net/ice/base/ice_common.c
> b/drivers/net/ice/base/ice_common.c
> index 5b4a13a41..7f7f4dad0 100644
> --- a/drivers/net/ice/base/ice_common.c
> +++ b/drivers/net/ice/base/ice_common.c
> @@ -2552,6 +2552,53 @@ ice_cache_phy_user_req(struct ice_port_info *pi,
> }
> }
>
> +/**
> + * ice_caps_to_fc_mode
> + * @caps: PHY capabilities
> + *
> + * Convert PHY FC capabilities to ice FC mode */ enum ice_fc_mode
> +ice_caps_to_fc_mode(u8 caps) {
> + if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE &&
> + caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE)
> + return ICE_FC_FULL;
> +
> + if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE)
> + return ICE_FC_TX_PAUSE;
> +
> + if (caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE)
> + return ICE_FC_RX_PAUSE;
> +
> + return ICE_FC_NONE;
> +}
> +
> +/**
> + * ice_caps_to_fec_mode
> + * @caps: PHY capabilities
> + * @fec_options: Link FEC options
> + *
> + * Convert PHY FEC capabilities to ice FEC mode */ enum ice_fec_mode
> +ice_caps_to_fec_mode(u8 caps, u8 fec_options) {
> + if (caps & ICE_AQC_PHY_EN_AUTO_FEC)
> + return ICE_FEC_AUTO;
> +
> + if (fec_options & (ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN |
> + ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ |
> + ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN |
> + ICE_AQC_PHY_FEC_25G_KR_REQ))
> + return ICE_FEC_BASER;
> +
> + if (fec_options & (ICE_AQC_PHY_FEC_25G_RS_528_REQ |
> + ICE_AQC_PHY_FEC_25G_RS_544_REQ |
> + ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN))
> + return ICE_FEC_RS;
> +
> + return ICE_FEC_NONE;
> +}
> +
Is there DPDK code to call the above functions? If not, then drop this patch.
> /**
> * ice_set_fc
> * @pi: port information structure
> @@ -2658,6 +2705,42 @@ ice_set_fc(struct ice_port_info *pi, u8
> *aq_failures, bool ena_auto_link_update)
> return status;
> }
>
> +/**
> + * ice_phy_caps_equals_cfg
> + * @phy_caps: PHY capabilities
> + * @phy_cfg: PHY configuration
> + *
> + * Helper function to determine if PHY capabilities matches PHY
> + * configuration
> + */
> +bool
> +ice_phy_caps_equals_cfg(struct ice_aqc_get_phy_caps_data *phy_caps,
> + struct ice_aqc_set_phy_cfg_data *phy_cfg) {
> + u8 caps_mask, cfg_mask;
> +
> + if (!phy_caps || !phy_cfg)
> + return false;
> +
> + /* These bits are not common between capabilities and
> configuration.
> + * Do not use them to determine equality.
> + */
> + caps_mask = ICE_AQC_PHY_CAPS_MASK &
> ~(ICE_AQC_PHY_AN_MODE |
> + ICE_AQC_PHY_EN_MOD_QUAL);
> + cfg_mask = ICE_AQ_PHY_ENA_VALID_MASK &
> ~ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
> +
> + if (phy_caps->phy_type_low != phy_cfg->phy_type_low ||
> + phy_caps->phy_type_high != phy_cfg->phy_type_high ||
> + ((phy_caps->caps & caps_mask) != (phy_cfg->caps & cfg_mask)) ||
> + phy_caps->low_power_ctrl != phy_cfg->low_power_ctrl ||
> + phy_caps->eee_cap != phy_cfg->eee_cap ||
> + phy_caps->eeer_value != phy_cfg->eeer_value ||
> + phy_caps->link_fec_options != phy_cfg->link_fec_opt)
> + return false;
> +
> + return true;
> +}
> +
> /**
> * ice_copy_phy_caps_to_cfg - Copy PHY ability data to configuration data
> * @caps: PHY ability structure to copy date from diff --git
> a/drivers/net/ice/base/ice_common.h
> b/drivers/net/ice/base/ice_common.h
> index 4cd87fc1e..10131b473 100644
> --- a/drivers/net/ice/base/ice_common.h
> +++ b/drivers/net/ice/base/ice_common.h
> @@ -136,14 +136,19 @@ enum ice_status ice_clear_pf_cfg(struct ice_hw
> *hw); enum ice_status ice_aq_set_phy_cfg(struct ice_hw *hw, struct
> ice_port_info *pi,
> struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd
> *cd);
> +enum ice_fc_mode ice_caps_to_fc_mode(u8 caps); enum ice_fec_mode
> +ice_caps_to_fec_mode(u8 caps, u8 fec_options);
> enum ice_status
> ice_set_fc(struct ice_port_info *pi, u8 *aq_failures,
> bool ena_auto_link_update);
> -void
> -ice_cfg_phy_fec(struct ice_aqc_set_phy_cfg_data *cfg, enum
> ice_fec_mode fec);
> +bool
> +ice_phy_caps_equals_cfg(struct ice_aqc_get_phy_caps_data *caps,
> + struct ice_aqc_set_phy_cfg_data *cfg);
> void
> ice_copy_phy_caps_to_cfg(struct ice_aqc_get_phy_caps_data *caps,
> struct ice_aqc_set_phy_cfg_data *cfg);
> +void
> +ice_cfg_phy_fec(struct ice_aqc_set_phy_cfg_data *cfg, enum
> ice_fec_mode
> +fec);
> enum ice_status
> ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link,
> struct ice_sq_cd *cd);
> --
> 2.17.1
> -----Original Message-----
> From: Stillwell Jr, Paul M
> Sent: Wednesday, June 12, 2019 12:27 AM
> To: Rong, Leyi <leyi.rong@intel.com>; Zhang, Qi Z <qi.z.zhang@intel.com>
> Cc: dev@dpdk.org; Nguyen, Anthony L <anthony.l.nguyen@intel.com>
> Subject: RE: [PATCH v2 21/66] net/ice/base: add helper functions for PHY caching
>
> > -----Original Message-----
> > From: Rong, Leyi
> > Sent: Tuesday, June 11, 2019 8:52 AM
> > To: Zhang, Qi Z <qi.z.zhang@intel.com>
> > Cc: dev@dpdk.org; Rong, Leyi <leyi.rong@intel.com>; Nguyen, Anthony L
> > <anthony.l.nguyen@intel.com>; Stillwell Jr, Paul M
> > <paul.m.stillwell.jr@intel.com>
> > Subject: [PATCH v2 21/66] net/ice/base: add helper functions for PHY
> > caching
> >
> > Add additional functions to aide in caching PHY configuration.
> > In order to cache the initial modes, we need to determine the
> > operating mode based on capabilities. Add helper functions for flow
> > control and FEC to take a set of capabilities and return the operating
> > mode matching those capabilities. Also add a helper function to
> > determine whether a PHY capability matches a PHY configuration.
> >
> > Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
> > Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
> > Signed-off-by: Leyi Rong <leyi.rong@intel.com>
> > ---
> > drivers/net/ice/base/ice_adminq_cmd.h | 1 +
> > drivers/net/ice/base/ice_common.c | 83
> > +++++++++++++++++++++++++++
> > drivers/net/ice/base/ice_common.h | 9 ++-
> > 3 files changed, 91 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/net/ice/base/ice_adminq_cmd.h
> > b/drivers/net/ice/base/ice_adminq_cmd.h
> > index 739f79e88..77f93b950 100644
> > --- a/drivers/net/ice/base/ice_adminq_cmd.h
> > +++ b/drivers/net/ice/base/ice_adminq_cmd.h
> > @@ -1594,6 +1594,7 @@ struct ice_aqc_get_link_status_data {
> > #define ICE_AQ_LINK_PWR_QSFP_CLASS_3 2
> > #define ICE_AQ_LINK_PWR_QSFP_CLASS_4 3
> > __le16 link_speed;
> > +#define ICE_AQ_LINK_SPEED_M 0x7FF
> > #define ICE_AQ_LINK_SPEED_10MB BIT(0)
> > #define ICE_AQ_LINK_SPEED_100MB BIT(1)
> > #define ICE_AQ_LINK_SPEED_1000MB BIT(2)
> > diff --git a/drivers/net/ice/base/ice_common.c
> > b/drivers/net/ice/base/ice_common.c
> > index 5b4a13a41..7f7f4dad0 100644
> > --- a/drivers/net/ice/base/ice_common.c
> > +++ b/drivers/net/ice/base/ice_common.c
> > @@ -2552,6 +2552,53 @@ ice_cache_phy_user_req(struct ice_port_info *pi,
> > }
> > }
> >
> > +/**
> > + * ice_caps_to_fc_mode
> > + * @caps: PHY capabilities
> > + *
> > + * Convert PHY FC capabilities to ice FC mode */ enum ice_fc_mode
> > +ice_caps_to_fc_mode(u8 caps) {
> > + if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE &&
> > + caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE)
> > + return ICE_FC_FULL;
> > +
> > + if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE)
> > + return ICE_FC_TX_PAUSE;
> > +
> > + if (caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE)
> > + return ICE_FC_RX_PAUSE;
> > +
> > + return ICE_FC_NONE;
> > +}
> > +
> > +/**
> > + * ice_caps_to_fec_mode
> > + * @caps: PHY capabilities
> > + * @fec_options: Link FEC options
> > + *
> > + * Convert PHY FEC capabilities to ice FEC mode */ enum ice_fec_mode
> > +ice_caps_to_fec_mode(u8 caps, u8 fec_options) {
> > + if (caps & ICE_AQC_PHY_EN_AUTO_FEC)
> > + return ICE_FEC_AUTO;
> > +
> > + if (fec_options & (ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN |
> > + ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ |
> > + ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN |
> > + ICE_AQC_PHY_FEC_25G_KR_REQ))
> > + return ICE_FEC_BASER;
> > +
> > + if (fec_options & (ICE_AQC_PHY_FEC_25G_RS_528_REQ |
> > + ICE_AQC_PHY_FEC_25G_RS_544_REQ |
> > + ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN))
> > + return ICE_FEC_RS;
> > +
> > + return ICE_FEC_NONE;
> > +}
> > +
>
> Is there DPDK code to call the above functions? If not, then drop this patch.
>
They will not be called.
@@ -1594,6 +1594,7 @@ struct ice_aqc_get_link_status_data {
#define ICE_AQ_LINK_PWR_QSFP_CLASS_3 2
#define ICE_AQ_LINK_PWR_QSFP_CLASS_4 3
__le16 link_speed;
+#define ICE_AQ_LINK_SPEED_M 0x7FF
#define ICE_AQ_LINK_SPEED_10MB BIT(0)
#define ICE_AQ_LINK_SPEED_100MB BIT(1)
#define ICE_AQ_LINK_SPEED_1000MB BIT(2)
@@ -2552,6 +2552,53 @@ ice_cache_phy_user_req(struct ice_port_info *pi,
}
}
+/**
+ * ice_caps_to_fc_mode
+ * @caps: PHY capabilities
+ *
+ * Convert PHY FC capabilities to ice FC mode
+ */
+enum ice_fc_mode ice_caps_to_fc_mode(u8 caps)
+{
+ if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE &&
+ caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE)
+ return ICE_FC_FULL;
+
+ if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE)
+ return ICE_FC_TX_PAUSE;
+
+ if (caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE)
+ return ICE_FC_RX_PAUSE;
+
+ return ICE_FC_NONE;
+}
+
+/**
+ * ice_caps_to_fec_mode
+ * @caps: PHY capabilities
+ * @fec_options: Link FEC options
+ *
+ * Convert PHY FEC capabilities to ice FEC mode
+ */
+enum ice_fec_mode ice_caps_to_fec_mode(u8 caps, u8 fec_options)
+{
+ if (caps & ICE_AQC_PHY_EN_AUTO_FEC)
+ return ICE_FEC_AUTO;
+
+ if (fec_options & (ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN |
+ ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ |
+ ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN |
+ ICE_AQC_PHY_FEC_25G_KR_REQ))
+ return ICE_FEC_BASER;
+
+ if (fec_options & (ICE_AQC_PHY_FEC_25G_RS_528_REQ |
+ ICE_AQC_PHY_FEC_25G_RS_544_REQ |
+ ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN))
+ return ICE_FEC_RS;
+
+ return ICE_FEC_NONE;
+}
+
/**
* ice_set_fc
* @pi: port information structure
@@ -2658,6 +2705,42 @@ ice_set_fc(struct ice_port_info *pi, u8 *aq_failures, bool ena_auto_link_update)
return status;
}
+/**
+ * ice_phy_caps_equals_cfg
+ * @phy_caps: PHY capabilities
+ * @phy_cfg: PHY configuration
+ *
+ * Helper function to determine if PHY capabilities matches PHY
+ * configuration
+ */
+bool
+ice_phy_caps_equals_cfg(struct ice_aqc_get_phy_caps_data *phy_caps,
+ struct ice_aqc_set_phy_cfg_data *phy_cfg)
+{
+ u8 caps_mask, cfg_mask;
+
+ if (!phy_caps || !phy_cfg)
+ return false;
+
+ /* These bits are not common between capabilities and configuration.
+ * Do not use them to determine equality.
+ */
+ caps_mask = ICE_AQC_PHY_CAPS_MASK & ~(ICE_AQC_PHY_AN_MODE |
+ ICE_AQC_PHY_EN_MOD_QUAL);
+ cfg_mask = ICE_AQ_PHY_ENA_VALID_MASK & ~ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
+
+ if (phy_caps->phy_type_low != phy_cfg->phy_type_low ||
+ phy_caps->phy_type_high != phy_cfg->phy_type_high ||
+ ((phy_caps->caps & caps_mask) != (phy_cfg->caps & cfg_mask)) ||
+ phy_caps->low_power_ctrl != phy_cfg->low_power_ctrl ||
+ phy_caps->eee_cap != phy_cfg->eee_cap ||
+ phy_caps->eeer_value != phy_cfg->eeer_value ||
+ phy_caps->link_fec_options != phy_cfg->link_fec_opt)
+ return false;
+
+ return true;
+}
+
/**
* ice_copy_phy_caps_to_cfg - Copy PHY ability data to configuration data
* @caps: PHY ability structure to copy date from
@@ -136,14 +136,19 @@ enum ice_status ice_clear_pf_cfg(struct ice_hw *hw);
enum ice_status
ice_aq_set_phy_cfg(struct ice_hw *hw, struct ice_port_info *pi,
struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd);
+enum ice_fc_mode ice_caps_to_fc_mode(u8 caps);
+enum ice_fec_mode ice_caps_to_fec_mode(u8 caps, u8 fec_options);
enum ice_status
ice_set_fc(struct ice_port_info *pi, u8 *aq_failures,
bool ena_auto_link_update);
-void
-ice_cfg_phy_fec(struct ice_aqc_set_phy_cfg_data *cfg, enum ice_fec_mode fec);
+bool
+ice_phy_caps_equals_cfg(struct ice_aqc_get_phy_caps_data *caps,
+ struct ice_aqc_set_phy_cfg_data *cfg);
void
ice_copy_phy_caps_to_cfg(struct ice_aqc_get_phy_caps_data *caps,
struct ice_aqc_set_phy_cfg_data *cfg);
+void
+ice_cfg_phy_fec(struct ice_aqc_set_phy_cfg_data *cfg, enum ice_fec_mode fec);
enum ice_status
ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link,
struct ice_sq_cd *cd);