From patchwork Sun Jun 2 15:23:43 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jerin Jacob Kollanukkaran X-Patchwork-Id: 54063 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 9993D1B996; Sun, 2 Jun 2019 17:25:00 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by dpdk.org (Postfix) with ESMTP id CD9801B995 for ; Sun, 2 Jun 2019 17:24:59 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x52FKPI7020378; Sun, 2 Jun 2019 08:24:59 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0818; bh=rgRY58DKQ0oPH1/EQtidCnldwClF/TQaxcCeMLuNL9Q=; b=VY41iW8Jns1ZJGEPQ/hzHsGIZ+7gBm4oE5Hkx7at4nTcz5Cky+LuzJ+VPF5oYAX88GLp 57F9ghU9NN6vN3L6OKpgVzBlWU4YHD0uYs3K/eKa2rb77KACoIHsgx7e2ChUGn0aCOUw ZyXJe1T+0QntsUF5ZAcS1RXQ2HzFZ6ZQGSb9w3K4xkOKAXYa1hhLTeCiF8lHlRsD6rnu FovK+aHziQxP60irlzzaBtiBZ9x0fRilqCjvyzQUz6pBK+yPiiVQ8n4rPXBX/SRQxBTQ crIeqsWHtrHo4Q1gr1pddKlprrBtYBH0i7TNQpn1BYmm0TaBHAW9GaEJha9c4NoG7UcU ww== Received: from sc-exch03.marvell.com ([199.233.58.183]) by mx0b-0016f401.pphosted.com with ESMTP id 2survk491h-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Sun, 02 Jun 2019 08:24:59 -0700 Received: from SC-EXCH03.marvell.com (10.93.176.83) by SC-EXCH03.marvell.com (10.93.176.83) with Microsoft SMTP Server (TLS) id 15.0.1367.3; Sun, 2 Jun 2019 08:24:57 -0700 Received: from maili.marvell.com (10.93.176.43) by SC-EXCH03.marvell.com (10.93.176.83) with Microsoft SMTP Server id 15.0.1367.3 via Frontend Transport; Sun, 2 Jun 2019 08:24:57 -0700 Received: from jerin-lab.marvell.com (jerin-lab.marvell.com [10.28.34.14]) by maili.marvell.com (Postfix) with ESMTP id 388473F703F; Sun, 2 Jun 2019 08:24:56 -0700 (PDT) From: To: , Jerin Jacob , Nithin Dabilpuram , Kiran Kumar K CC: , Vamsi Attunuru Date: Sun, 2 Jun 2019 20:53:43 +0530 Message-ID: <20190602152434.23996-8-jerinj@marvell.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190602152434.23996-1-jerinj@marvell.com> References: <20190602152434.23996-1-jerinj@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-06-02_09:, , signatures=0 Subject: [dpdk-dev] [PATCH v1 07/58] net/octeontx2: add device configure operation X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Jerin Jacob Add device configure operation. This would call lf_alloc mailbox to allocate a NIX LF and upon return, AF will return the attributes for the select LF. Signed-off-by: Jerin Jacob Signed-off-by: Vamsi Attunuru Signed-off-by: Nithin Dabilpuram --- drivers/net/octeontx2/otx2_ethdev.c | 151 ++++++++++++++++++++++++++++ drivers/net/octeontx2/otx2_ethdev.h | 11 ++ 2 files changed, 162 insertions(+) diff --git a/drivers/net/octeontx2/otx2_ethdev.c b/drivers/net/octeontx2/otx2_ethdev.c index 6e3c70559..65d72a47f 100644 --- a/drivers/net/octeontx2/otx2_ethdev.c +++ b/drivers/net/octeontx2/otx2_ethdev.c @@ -39,6 +39,52 @@ nix_get_tx_offload_capa(struct otx2_eth_dev *dev) return NIX_TX_OFFLOAD_CAPA; } +static int +nix_lf_alloc(struct otx2_eth_dev *dev, uint32_t nb_rxq, uint32_t nb_txq) +{ + struct otx2_mbox *mbox = dev->mbox; + struct nix_lf_alloc_req *req; + struct nix_lf_alloc_rsp *rsp; + int rc; + + req = otx2_mbox_alloc_msg_nix_lf_alloc(mbox); + req->rq_cnt = nb_rxq; + req->sq_cnt = nb_txq; + req->cq_cnt = nb_rxq; + /* XQE_SZ should be in Sync with NIX_CQ_ENTRY_SZ */ + RTE_BUILD_BUG_ON(NIX_CQ_ENTRY_SZ != 128); + req->xqe_sz = NIX_XQESZ_W16; + req->rss_sz = dev->rss_info.rss_size; + req->rss_grps = NIX_RSS_GRPS; + req->npa_func = otx2_npa_pf_func_get(); + req->sso_func = otx2_sso_pf_func_get(); + req->rx_cfg = BIT_ULL(35 /* DIS_APAD */); + if (dev->rx_offloads & (DEV_RX_OFFLOAD_TCP_CKSUM | + DEV_RX_OFFLOAD_UDP_CKSUM)) { + req->rx_cfg |= BIT_ULL(37 /* CSUM_OL4 */); + req->rx_cfg |= BIT_ULL(36 /* CSUM_IL4 */); + } + + rc = otx2_mbox_process_msg(mbox, (void *)&rsp); + if (rc) + return rc; + + dev->sqb_size = rsp->sqb_size; + dev->tx_chan_base = rsp->tx_chan_base; + dev->rx_chan_base = rsp->rx_chan_base; + dev->rx_chan_cnt = rsp->rx_chan_cnt; + dev->tx_chan_cnt = rsp->tx_chan_cnt; + dev->lso_tsov4_idx = rsp->lso_tsov4_idx; + dev->lso_tsov6_idx = rsp->lso_tsov6_idx; + dev->lf_tx_stats = rsp->lf_tx_stats; + dev->lf_rx_stats = rsp->lf_rx_stats; + dev->cints = rsp->cints; + dev->qints = rsp->qints; + dev->npc_flow.channel = dev->rx_chan_base; + + return 0; +} + static int nix_lf_free(struct otx2_eth_dev *dev) { @@ -64,9 +110,114 @@ nix_lf_free(struct otx2_eth_dev *dev) return otx2_mbox_process(mbox); } +static int +otx2_nix_configure(struct rte_eth_dev *eth_dev) +{ + struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev); + struct rte_eth_dev_data *data = eth_dev->data; + struct rte_eth_conf *conf = &data->dev_conf; + struct rte_eth_rxmode *rxmode = &conf->rxmode; + struct rte_eth_txmode *txmode = &conf->txmode; + char ea_fmt[RTE_ETHER_ADDR_FMT_SIZE]; + struct rte_ether_addr *ea; + uint8_t nb_rxq, nb_txq; + int rc; + + rc = -EINVAL; + + /* Sanity checks */ + if (rte_eal_has_hugepages() == 0) { + otx2_err("Huge page is not configured"); + goto fail; + } + + if (rte_eal_iova_mode() != RTE_IOVA_VA) { + otx2_err("iova mode should be va"); + goto fail; + } + + if (conf->link_speeds & ETH_LINK_SPEED_FIXED) { + otx2_err("Setting link speed/duplex not supported"); + goto fail; + } + + if (conf->dcb_capability_en == 1) { + otx2_err("dcb enable is not supported"); + goto fail; + } + + if (conf->fdir_conf.mode != RTE_FDIR_MODE_NONE) { + otx2_err("Flow director is not supported"); + goto fail; + } + + if (rxmode->mq_mode != ETH_MQ_RX_NONE && + rxmode->mq_mode != ETH_MQ_RX_RSS) { + otx2_err("Unsupported mq rx mode %d", rxmode->mq_mode); + goto fail; + } + + if (txmode->mq_mode != ETH_MQ_TX_NONE) { + otx2_err("Unsupported mq tx mode %d", txmode->mq_mode); + goto fail; + } + + /* Free the resources allocated from the previous configure */ + if (dev->configured == 1) + nix_lf_free(dev); + + if (otx2_dev_is_A0(dev) && + (txmode->offloads & DEV_TX_OFFLOAD_SCTP_CKSUM) && + ((txmode->offloads & DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM) || + (txmode->offloads & DEV_TX_OFFLOAD_OUTER_UDP_CKSUM))) { + otx2_err("Outer IP and SCTP checksum unsupported"); + rc = -EINVAL; + goto fail; + } + + dev->rx_offloads = rxmode->offloads; + dev->tx_offloads = txmode->offloads; + dev->rss_info.rss_grps = NIX_RSS_GRPS; + + nb_rxq = RTE_MAX(data->nb_rx_queues, 1); + nb_txq = RTE_MAX(data->nb_tx_queues, 1); + + /* Alloc a nix lf */ + rc = nix_lf_alloc(dev, nb_rxq, nb_txq); + if (rc) { + otx2_err("Failed to init nix_lf rc=%d", rc); + goto fail; + } + + /* Update the mac address */ + ea = eth_dev->data->mac_addrs; + memcpy(ea, dev->mac_addr, RTE_ETHER_ADDR_LEN); + if (rte_is_zero_ether_addr(ea)) + rte_eth_random_addr((uint8_t *)ea); + + rte_ether_format_addr(ea_fmt, RTE_ETHER_ADDR_FMT_SIZE, ea); + + otx2_nix_dbg("Configured port%d mac=%s nb_rxq=%d nb_txq=%d" + " rx_offloads=0x%" PRIx64 " tx_offloads=0x%" PRIx64 "" + " rx_flags=0x%x tx_flags=0x%x", + eth_dev->data->port_id, ea_fmt, nb_rxq, + nb_txq, dev->rx_offloads, dev->tx_offloads, + dev->rx_offload_flags, dev->tx_offload_flags); + + /* All good */ + dev->configured = 1; + dev->configured_nb_rx_qs = data->nb_rx_queues; + dev->configured_nb_tx_qs = data->nb_tx_queues; + return 0; + +fail: + return rc; +} + /* Initialize and register driver with DPDK Application */ static const struct eth_dev_ops otx2_eth_dev_ops = { .dev_infos_get = otx2_nix_info_get, + .dev_configure = otx2_nix_configure, }; static inline int diff --git a/drivers/net/octeontx2/otx2_ethdev.h b/drivers/net/octeontx2/otx2_ethdev.h index 00baabaac..27cad971c 100644 --- a/drivers/net/octeontx2/otx2_ethdev.h +++ b/drivers/net/octeontx2/otx2_ethdev.h @@ -39,11 +39,14 @@ #define NIX_MAX_HW_MTU 9190 #define NIX_MAX_HW_FRS (NIX_MAX_HW_MTU + NIX_HW_L2_OVERHEAD) #define NIX_MIN_HW_FRS 60 +/* Group 0 will be used for RSS, 1 -7 will be used for rte_flow RSS action*/ +#define NIX_RSS_GRPS 8 #define NIX_HASH_KEY_SIZE 48 /* 352 Bits */ #define NIX_RSS_RETA_SIZE 64 #define NIX_RX_MIN_DESC 16 #define NIX_RX_MIN_DESC_ALIGN 16 #define NIX_RX_NB_SEG_MAX 6 +#define NIX_CQ_ENTRY_SZ 128 /* If PTP is enabled additional SEND MEM DESC is required which * takes 2 words, hence max 7 iova address are possible @@ -85,9 +88,11 @@ struct otx2_rss_info { uint16_t rss_size; + uint8_t rss_grps; }; struct otx2_npc_flow_info { + uint16_t channel; /*rx channel */ uint16_t flow_prealloc_size; uint16_t flow_max_priority; }; @@ -104,7 +109,13 @@ struct otx2_eth_dev { uint8_t lso_tsov6_idx; uint8_t mac_addr[RTE_ETHER_ADDR_LEN]; uint8_t max_mac_entries; + uint8_t lf_tx_stats; + uint8_t lf_rx_stats; + uint16_t cints; + uint16_t qints; uint8_t configured; + uint8_t configured_nb_rx_qs; + uint8_t configured_nb_tx_qs; uint16_t nix_msixoff; uintptr_t base; uintptr_t lmt_addr;