From patchwork Sat Jun 1 18:53:12 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pavan Nikhilesh Bhagavatula X-Patchwork-Id: 54013 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 3D8BA1B952; Sat, 1 Jun 2019 20:55:47 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by dpdk.org (Postfix) with ESMTP id D5C2B2C60 for ; Sat, 1 Jun 2019 20:55:39 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x51ItbrX030054 for ; Sat, 1 Jun 2019 11:55:39 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0818; bh=dooWT1712FVtM0en9YKuX9x8jcqvMnFRUQv2sNjvaUg=; b=UqDXqgkfId58Dhha7Wzb3hx0l1cSVw128u27kD5AfPe7MfYOZrzcjykDEeSnadC5C1kC MpIUmi0552aCU9nUZMLHiAiOa+acfdGqPQyL7yOFtYPjgX+rusgJs9yuoH4U08NwCcN3 C+TVHva3Qky12T2G+zxBUiTE7itv9uVlAFmDRczjkXHQSrb9m9dPHJflrpZFoFMS67+D opuEFYrroFN8sK5W5ED9e9h4wou54Qupi0Mv0Q0u8Ornd4CUJjmM40LSx5ydIZdN73WC /wFmJnn9gPOYc9aev/FvxnC4K72+pYiblNhdeT4om+mxIdlkW1Y5kMU9S1Lh4KuVfbGs bw== Received: from sc-exch02.marvell.com ([199.233.58.182]) by mx0b-0016f401.pphosted.com with ESMTP id 2survk12dg-3 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Sat, 01 Jun 2019 11:55:38 -0700 Received: from SC-EXCH01.marvell.com (10.93.176.81) by SC-EXCH02.marvell.com (10.93.176.82) with Microsoft SMTP Server (TLS) id 15.0.1367.3; Sat, 1 Jun 2019 11:55:35 -0700 Received: from maili.marvell.com (10.93.176.43) by SC-EXCH01.marvell.com (10.93.176.81) with Microsoft SMTP Server id 15.0.1367.3 via Frontend Transport; Sat, 1 Jun 2019 11:55:35 -0700 Received: from BG-LT7430.marvell.com (unknown [10.28.17.28]) by maili.marvell.com (Postfix) with ESMTP id 0C25A3F70E4; Sat, 1 Jun 2019 11:54:58 -0700 (PDT) From: To: , Pavan Nikhilesh CC: , Nithin Dabilpuram Date: Sun, 2 Jun 2019 00:23:12 +0530 Message-ID: <20190601185355.370-3-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190601185355.370-1-pbhagavatula@marvell.com> References: <20190601185355.370-1-pbhagavatula@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-06-01_13:, , signatures=0 Subject: [dpdk-dev] [PATCH 02/44] event/octeontx2: add init and fini for octeontx2 SSO object X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Pavan Nikhilesh SSO object needs to be initialized to communicate with the kernel AF driver through mbox using the common API's. Also, initialize the internal eventdev structure to defaults. Attach NPA lf to the PF if needed. Signed-off-by: Jerin Jacob Signed-off-by: Pavan Nikhilesh Signed-off-by: Nithin Dabilpuram Acked-by: Jerin Jacob --- drivers/event/octeontx2/Makefile | 2 +- drivers/event/octeontx2/meson.build | 2 +- drivers/event/octeontx2/otx2_evdev.c | 85 +++++++++++++++++++++++++++- drivers/event/octeontx2/otx2_evdev.h | 22 ++++++- 4 files changed, 106 insertions(+), 5 deletions(-) diff --git a/drivers/event/octeontx2/Makefile b/drivers/event/octeontx2/Makefile index dbf6ec22d..36f0b2b12 100644 --- a/drivers/event/octeontx2/Makefile +++ b/drivers/event/octeontx2/Makefile @@ -34,6 +34,6 @@ SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_EVENTDEV) += otx2_evdev.c LDLIBS += -lrte_eal -lrte_bus_pci -lrte_pci LDLIBS += -lrte_eventdev -LDLIBS += -lrte_common_octeontx2 +LDLIBS += -lrte_common_octeontx2 -lrte_mempool_octeontx2 include $(RTE_SDK)/mk/rte.lib.mk diff --git a/drivers/event/octeontx2/meson.build b/drivers/event/octeontx2/meson.build index c4f442174..3fc96421d 100644 --- a/drivers/event/octeontx2/meson.build +++ b/drivers/event/octeontx2/meson.build @@ -18,4 +18,4 @@ foreach flag: extra_flags endif endforeach -deps += ['bus_pci', 'common_octeontx2'] +deps += ['bus_pci', 'common_octeontx2', 'mempool_octeontx2'] diff --git a/drivers/event/octeontx2/otx2_evdev.c b/drivers/event/octeontx2/otx2_evdev.c index faffd3f0c..15190af9e 100644 --- a/drivers/event/octeontx2/otx2_evdev.c +++ b/drivers/event/octeontx2/otx2_evdev.c @@ -46,22 +46,103 @@ static struct rte_pci_driver pci_sso = { int otx2_sso_init(struct rte_eventdev *event_dev) { - RTE_SET_USED(event_dev); + struct free_rsrcs_rsp *rsrc_cnt; + struct rte_pci_device *pci_dev; + struct otx2_sso_evdev *dev; + int rc; + /* For secondary processes, the primary has done all the work */ if (rte_eal_process_type() != RTE_PROC_PRIMARY) return 0; + dev = sso_pmd_priv(event_dev); + + pci_dev = container_of(event_dev->dev, struct rte_pci_device, device); + + /* Initialize the base otx2_dev object */ + rc = otx2_dev_init(pci_dev, dev); + if (rc < 0) { + otx2_err("failed to initialize otx2_dev rc=%d", rc); + goto error; + } + + /* Get SSO and SSOW MSIX rsrc cnt */ + otx2_mbox_alloc_msg_free_rsrc_cnt(dev->mbox); + rc = otx2_mbox_process_msg(dev->mbox, (void *)&rsrc_cnt); + if (rc < 0) { + otx2_err("unable to get free rsrc count"); + goto otx2_dev_uninit; + } + otx2_sso_dbg("sso %d ssow %d npalf %d provisioned", rsrc_cnt->sso, + rsrc_cnt->ssow, rsrc_cnt->npa); + + dev->max_event_ports = RTE_MIN(rsrc_cnt->ssow, OTX2_SSO_MAX_VHWS); + dev->max_event_queues = RTE_MIN(rsrc_cnt->sso, OTX2_SSO_MAX_VHGRP); + /* Grab the NPA LF if required */ + rc = otx2_npa_lf_init(pci_dev, dev); + if (rc < 0) { + otx2_err("unable to init npalf. It might not be provisioned"); + goto otx2_dev_uninit; + } + + dev->drv_inited = true; + dev->is_timeout_deq = 0; + dev->min_dequeue_timeout_ns = USEC2NSEC(1); + dev->max_dequeue_timeout_ns = USEC2NSEC(0x3FF); + dev->max_num_events = -1; + dev->nb_event_queues = 0; + dev->nb_event_ports = 0; + + if (!dev->max_event_ports || !dev->max_event_queues) { + otx2_err("not enough eventdev resource queues=%d ports=%d", + dev->max_event_queues, dev->max_event_ports); + rc = -ENODEV; + goto otx2_npa_lf_uninit; + } + + otx2_sso_pf_func_set(dev->pf_func); + otx2_sso_dbg("initializing %s max_queues=%d max_ports=%d", + event_dev->data->name, dev->max_event_queues, + dev->max_event_ports); + + return 0; + +otx2_npa_lf_uninit: + otx2_npa_lf_fini(); +otx2_dev_uninit: + otx2_dev_fini(pci_dev, dev); +error: + return rc; } int otx2_sso_fini(struct rte_eventdev *event_dev) { - RTE_SET_USED(event_dev); + struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev); + struct rte_pci_device *pci_dev; + /* For secondary processes, nothing to be done */ if (rte_eal_process_type() != RTE_PROC_PRIMARY) return 0; + pci_dev = container_of(event_dev->dev, struct rte_pci_device, device); + + if (!dev->drv_inited) + goto dev_fini; + + dev->drv_inited = false; + otx2_npa_lf_fini(); + +dev_fini: + if (otx2_npa_lf_active(dev)) { + otx2_info("%s: common resource in use by other devices", + pci_dev->name); + return -EAGAIN; + } + + otx2_dev_fini(pci_dev, dev); + return 0; } diff --git a/drivers/event/octeontx2/otx2_evdev.h b/drivers/event/octeontx2/otx2_evdev.h index 1df233293..4427efcad 100644 --- a/drivers/event/octeontx2/otx2_evdev.h +++ b/drivers/event/octeontx2/otx2_evdev.h @@ -8,6 +8,8 @@ #include #include "otx2_common.h" +#include "otx2_dev.h" +#include "otx2_mempool.h" #define EVENTDEV_NAME_OCTEONTX2_PMD otx2_eventdev @@ -16,8 +18,26 @@ #define OTX2_SSO_MAX_VHGRP RTE_EVENT_MAX_QUEUES_PER_DEV #define OTX2_SSO_MAX_VHWS (UINT8_MAX) +#define USEC2NSEC(__us) ((__us) * 1E3) + struct otx2_sso_evdev { -}; + OTX2_DEV; /* Base class */ + uint8_t max_event_queues; + uint8_t max_event_ports; + uint8_t is_timeout_deq; + uint8_t nb_event_queues; + uint8_t nb_event_ports; + uint32_t deq_tmo_ns; + uint32_t min_dequeue_timeout_ns; + uint32_t max_dequeue_timeout_ns; + int32_t max_num_events; +} __rte_cache_aligned; + +static inline struct otx2_sso_evdev * +sso_pmd_priv(const struct rte_eventdev *event_dev) +{ + return event_dev->data->dev_private; +} /* Init and Fini API's */ int otx2_sso_init(struct rte_eventdev *event_dev);