[v2,1/1] net/e1000: set/clear GO_LINKD bit only if PHY reset is not blocked

Message ID 20190516220331.91984-2-shweta.choudaha@gmail.com
State New
Delegated to: xiaolong ye
Headers show
Series
  • net/e1000: set/clear GO_LINKD bit only if PHY reset is not blocked
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Checks

Context Check Description
ci/intel-Performance-Testing success Performance Testing PASS
ci/mellanox-Performance-Testing success Performance Testing PASS
ci/Intel-compilation success Compilation OK
ci/checkpatch success coding style OK

Commit Message

Shweta Choudaha May 16, 2019, 10:03 p.m.
From: Shweta Choudaha <shweta.choudaha@att.com>

When PHY reset is blocked as is the case when BMC is connected via NC-SI
do not set GO_LINKD bit in PHY power management register in dev_stop as
this will disconnect the PHY. Also, in dev_close clear the GO_LINKD
bit only if PHY reset is not blocked

Fixes: 3af34dec0b41 ("igb: force phy power up/down")
CC: stable@dpdk.org

Signed-off-by: Shweta Choudaha <shweta.choudaha@att.com>
---
 drivers/net/e1000/igb_ethdev.c | 10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)

Patch

diff --git a/drivers/net/e1000/igb_ethdev.c b/drivers/net/e1000/igb_ethdev.c
index d3a8f5bf4..4d4065d05 100644
--- a/drivers/net/e1000/igb_ethdev.c
+++ b/drivers/net/e1000/igb_ethdev.c
@@ -1515,8 +1515,9 @@  eth_igb_stop(struct rte_eth_dev *dev)
 	igb_pf_reset_hw(hw);
 	E1000_WRITE_REG(hw, E1000_WUC, 0);
 
-	/* Set bit for Go Link disconnect */
-	if (hw->mac.type >= e1000_82580) {
+	/* Set bit for Go Link disconnect if PHY reset is not blocked */
+	if (hw->mac.type >= e1000_82580 &&
+	    (e1000_check_reset_block(hw) != E1000_BLK_PHY_RESET)) {
 		uint32_t phpm_reg;
 
 		phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
@@ -1590,8 +1591,9 @@  eth_igb_close(struct rte_eth_dev *dev)
 	igb_release_manageability(hw);
 	igb_hw_control_release(hw);
 
-	/* Clear bit for Go Link disconnect */
-	if (hw->mac.type >= e1000_82580) {
+	/* Clear bit for Go Link disconnect if PHY reset is not blocked */
+	if (hw->mac.type >= e1000_82580 &&
+	    (e1000_check_reset_block(hw) != E1000_BLK_PHY_RESET)) {
 		uint32_t phpm_reg;
 
 		phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);