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DIR:OUT; SFP:1101; SCL:1; SRVR:VE1PR04MB6367; H:VE1PR04MB6365.eurprd04.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: xkjETgPk8MCfdeMJqInrmdSgD4gautolbMJ984c92bBDqMX8EJu9CYybigEkXmGMp4EMZKDL/XOMkpor+yLOpJeWEDkdXcia4iRYGwzbsptPfZgOh1fuSBPBSRzhk6uieChOvfgET0TvNsEmYHAc1eK3hLKMGZ6dFCIbadOVAR49hlGzMTI5W9haab5WzD8H/yBpQqlvz1dycsr35VPZnJJcMrwqNc4MSDApoCEN+zkFOUiz+akXmgASN1rCrm2jeDfheq1TU7AlHohYfw2SUhYYL09UOjP6NRnWCQYDY1hsr/Q27LkloHJuC1+PiXXsJAWojXjTJ9eEXmdNkaNNDV/sDDBYCgIfT5Y5TFZ2e7ryiS8v74CzEDofU2feCEWSu//Q5FhQ6rv1OCyhtWycXwVq3KZHoyK9rU/RRuCllEY= MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 7fd41a15-80ab-44da-927d-08d6bf427122 X-MS-Exchange-CrossTenant-originalarrivaltime: 12 Apr 2019 12:29:01.0204 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-Transport-CrossTenantHeadersStamped: VE1PR04MB6367 Subject: [dpdk-dev] [PATCH v4 06/13] net/enetc: replace register read/write macros with functions X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Replacing read-write macros with already available read-write functions. Signed-off-by: Gagandeep Singh --- drivers/net/enetc/enetc.h | 7 +--- drivers/net/enetc/enetc_ethdev.c | 61 ++++++++++++++++---------------- 2 files changed, 31 insertions(+), 37 deletions(-) diff --git a/drivers/net/enetc/enetc.h b/drivers/net/enetc/enetc.h index 0e80d1c5b..56454dc9d 100644 --- a/drivers/net/enetc/enetc.h +++ b/drivers/net/enetc/enetc.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright 2018 NXP + * Copyright 2018-2019 NXP */ #ifndef _ENETC_H_ @@ -86,11 +86,6 @@ struct enetc_eth_adapter { #define ENETC_DEV_PRIVATE_TO_INTR(adapter) \ (&((struct enetc_eth_adapter *)adapter)->intr) -#define ENETC_GET_HW_ADDR(reg, addr) ((void *)(((size_t)reg) + (addr))) -#define ENETC_REG_READ(addr) (*(uint32_t *)addr) -#define ENETC_REG_WRITE(addr, val) (*(uint32_t *)addr = val) -#define ENETC_REG_WRITE_RELAXED(addr, val) (*(uint32_t *)addr = val) - /* * RX/TX ENETC function prototypes */ diff --git a/drivers/net/enetc/enetc_ethdev.c b/drivers/net/enetc/enetc_ethdev.c index 10b2b396d..2d8c4e604 100644 --- a/drivers/net/enetc/enetc_ethdev.c +++ b/drivers/net/enetc/enetc_ethdev.c @@ -131,28 +131,31 @@ enetc_dev_start(struct rte_eth_dev *dev) { struct enetc_eth_hw *hw = ENETC_DEV_PRIVATE_TO_HW(dev->data->dev_private); + struct enetc_hw *enetc_hw = &hw->hw; uint32_t val; PMD_INIT_FUNC_TRACE(); - val = ENETC_REG_READ(ENETC_GET_HW_ADDR(hw->hw.port, - ENETC_PM0_CMD_CFG)); - ENETC_REG_WRITE(ENETC_GET_HW_ADDR(hw->hw.port, ENETC_PM0_CMD_CFG), - val | ENETC_PM0_TX_EN | ENETC_PM0_RX_EN); + val = enetc_port_rd(enetc_hw, ENETC_PM0_CMD_CFG); + enetc_port_wr(enetc_hw, ENETC_PM0_CMD_CFG, + val | ENETC_PM0_TX_EN | ENETC_PM0_RX_EN); /* Enable port */ - val = ENETC_REG_READ(ENETC_GET_HW_ADDR(hw->hw.port, ENETC_PMR)); - ENETC_REG_WRITE(ENETC_GET_HW_ADDR(hw->hw.port, ENETC_PMR), - val | ENETC_PMR_EN); + val = enetc_port_rd(enetc_hw, ENETC_PMR); + enetc_port_wr(enetc_hw, ENETC_PMR, val | ENETC_PMR_EN); /* set auto-speed for RGMII */ - if (enetc_port_rd(&hw->hw, ENETC_PM0_IF_MODE) & ENETC_PMO_IFM_RG) { - enetc_port_wr(&hw->hw, ENETC_PM0_IF_MODE, ENETC_PM0_IFM_RGAUTO); - enetc_port_wr(&hw->hw, ENETC_PM1_IF_MODE, ENETC_PM0_IFM_RGAUTO); + if (enetc_port_rd(enetc_hw, ENETC_PM0_IF_MODE) & ENETC_PMO_IFM_RG) { + enetc_port_wr(enetc_hw, ENETC_PM0_IF_MODE, + ENETC_PM0_IFM_RGAUTO); + enetc_port_wr(enetc_hw, ENETC_PM1_IF_MODE, + ENETC_PM0_IFM_RGAUTO); } - if (enetc_global_rd(&hw->hw, + if (enetc_global_rd(enetc_hw, ENETC_G_EPFBLPR(1)) == ENETC_G_EPFBLPR1_XGMII) { - enetc_port_wr(&hw->hw, ENETC_PM0_IF_MODE, ENETC_PM0_IFM_XGMII); - enetc_port_wr(&hw->hw, ENETC_PM1_IF_MODE, ENETC_PM0_IFM_XGMII); + enetc_port_wr(enetc_hw, ENETC_PM0_IF_MODE, + ENETC_PM0_IFM_XGMII); + enetc_port_wr(enetc_hw, ENETC_PM1_IF_MODE, + ENETC_PM0_IFM_XGMII); } return 0; @@ -163,18 +166,17 @@ enetc_dev_stop(struct rte_eth_dev *dev) { struct enetc_eth_hw *hw = ENETC_DEV_PRIVATE_TO_HW(dev->data->dev_private); + struct enetc_hw *enetc_hw = &hw->hw; uint32_t val; PMD_INIT_FUNC_TRACE(); /* Disable port */ - val = ENETC_REG_READ(ENETC_GET_HW_ADDR(hw->hw.port, ENETC_PMR)); - ENETC_REG_WRITE(ENETC_GET_HW_ADDR(hw->hw.port, ENETC_PMR), - val & (~ENETC_PMR_EN)); - - val = ENETC_REG_READ(ENETC_GET_HW_ADDR(hw->hw.port, - ENETC_PM0_CMD_CFG)); - ENETC_REG_WRITE(ENETC_GET_HW_ADDR(hw->hw.port, ENETC_PM0_CMD_CFG), - val & (~(ENETC_PM0_TX_EN | ENETC_PM0_RX_EN))); + val = enetc_port_rd(enetc_hw, ENETC_PMR); + enetc_port_wr(enetc_hw, ENETC_PMR, val & (~ENETC_PMR_EN)); + + val = enetc_port_rd(enetc_hw, ENETC_PM0_CMD_CFG); + enetc_port_wr(enetc_hw, ENETC_PM0_CMD_CFG, + val & (~(ENETC_PM0_TX_EN | ENETC_PM0_RX_EN))); } static void @@ -221,6 +223,7 @@ enetc_link_update(struct rte_eth_dev *dev, int wait_to_complete __rte_unused) { struct enetc_eth_hw *hw = ENETC_DEV_PRIVATE_TO_HW(dev->data->dev_private); + struct enetc_hw *enetc_hw = &hw->hw; struct rte_eth_link link; uint32_t status; @@ -228,8 +231,7 @@ enetc_link_update(struct rte_eth_dev *dev, int wait_to_complete __rte_unused) memset(&link, 0, sizeof(link)); - status = ENETC_REG_READ(ENETC_GET_HW_ADDR(hw->hw.port, - ENETC_PM0_STATUS)); + status = enetc_port_rd(enetc_hw, ENETC_PM0_STATUS); if (status & ENETC_LINK_MODE) link.link_duplex = ETH_LINK_FULL_DUPLEX; @@ -262,6 +264,7 @@ static int enetc_hardware_init(struct enetc_eth_hw *hw) { uint32_t psipmr = 0; + struct enetc_hw *enetc_hw = &hw->hw; PMD_INIT_FUNC_TRACE(); /* Calculating and storing the base HW addresses */ @@ -269,8 +272,7 @@ enetc_hardware_init(struct enetc_eth_hw *hw) hw->hw.global = (void *)((size_t)hw->hw.reg + ENETC_GLOBAL_BASE); /* Enabling Station Interface */ - ENETC_REG_WRITE(ENETC_GET_HW_ADDR(hw->hw.reg, ENETC_SIMR), - ENETC_SIMR_EN); + enetc_wr(enetc_hw, ENETC_SIMR, ENETC_SIMR_EN); /* Setting to accept broadcast packets for each inetrface */ psipmr |= ENETC_PSIPMR_SET_UP(0) | ENETC_PSIPMR_SET_MP(0) | @@ -280,14 +282,11 @@ enetc_hardware_init(struct enetc_eth_hw *hw) psipmr |= ENETC_PSIPMR_SET_UP(2) | ENETC_PSIPMR_SET_MP(2) | ENETC_PSIPMR_SET_VLAN_MP(2); - ENETC_REG_WRITE(ENETC_GET_HW_ADDR(hw->hw.port, ENETC_PSIPMR), - psipmr); + enetc_port_wr(enetc_hw, ENETC_PSIPMR, psipmr); /* Enabling broadcast address */ - ENETC_REG_WRITE(ENETC_GET_HW_ADDR(hw->hw.port, ENETC_PSIPMAR0(0)), - 0xFFFFFFFF); - ENETC_REG_WRITE(ENETC_GET_HW_ADDR(hw->hw.port, ENETC_PSIPMAR1(0)), - 0xFFFF << 16); + enetc_port_wr(enetc_hw, ENETC_PSIPMAR0(0), 0xFFFFFFFF); + enetc_port_wr(enetc_hw, ENETC_PSIPMAR1(0), 0xFFFF << 16); return 0; }