[v2,11/15] raw/ifpga/base: add eth group driver
diff mbox series

Message ID 1553875099-166351-12-git-send-email-rosen.xu@intel.com
State Superseded, archived
Delegated to: Ferruh Yigit
Headers show
Series
  • Add patch set for IPN3KE
Related show

Checks

Context Check Description
ci/checkpatch success coding style OK
ci/Intel-compilation fail Compilation issues

Commit Message

Xu, Rosen March 29, 2019, 3:58 p.m. UTC
From: "Zhang, Tianfei" <tianfei.zhang@intel.com>

There is two eth group devices in PAC N3000 card,
each eth group include PHY device and MAC device. Exposing
APIs for DPDK PMD driver to access those devices.

Signed-off-by: Zhang, Tianfei <tianfei.zhang@intel.com>
---
 drivers/raw/ifpga_rawdev/base/Makefile            |   1 +
 drivers/raw/ifpga_rawdev/base/ifpga_api.c         |  74 ++++++-
 drivers/raw/ifpga_rawdev/base/ifpga_defines.h     |  39 ++++
 drivers/raw/ifpga_rawdev/base/ifpga_enumerate.c   |   6 +
 drivers/raw/ifpga_rawdev/base/ifpga_feature_dev.c |   2 +
 drivers/raw/ifpga_rawdev/base/ifpga_feature_dev.h |  12 ++
 drivers/raw/ifpga_rawdev/base/ifpga_fme.c         | 250 ++++++++++++++++++++++
 drivers/raw/ifpga_rawdev/base/ifpga_hw.h          |   7 +
 drivers/raw/ifpga_rawdev/base/meson.build         |   1 +
 drivers/raw/ifpga_rawdev/base/opae_eth_group.c    | 145 +++++++++++++
 drivers/raw/ifpga_rawdev/base/opae_eth_group.h    |  96 +++++++++
 drivers/raw/ifpga_rawdev/base/opae_hw_api.c       | 149 +++++++++++++
 drivers/raw/ifpga_rawdev/base/opae_hw_api.h       |  27 +++
 drivers/raw/ifpga_rawdev/base/opae_intel_max10.h  |  42 +++-
 drivers/raw/ifpga_rawdev/base/opae_osdep.h        |  16 +-
 15 files changed, 858 insertions(+), 9 deletions(-)
 create mode 100644 drivers/raw/ifpga_rawdev/base/opae_eth_group.c
 create mode 100644 drivers/raw/ifpga_rawdev/base/opae_eth_group.h

Patch
diff mbox series

diff --git a/drivers/raw/ifpga_rawdev/base/Makefile b/drivers/raw/ifpga_rawdev/base/Makefile
index edb538f..c5bbcbd 100644
--- a/drivers/raw/ifpga_rawdev/base/Makefile
+++ b/drivers/raw/ifpga_rawdev/base/Makefile
@@ -27,5 +27,6 @@  SRCS-y += opae_spi_transaction.c
 SRCS-y += opae_intel_max10.c
 SRCS-y += opae_i2c.c
 SRCS-y += opae_at24_eeprom.c
+SRCS-y += opae_eth_group.c
 
 SRCS-y += $(wildcard $(SRCDIR)/base/$(OSDEP)/*.c)
diff --git a/drivers/raw/ifpga_rawdev/base/ifpga_api.c b/drivers/raw/ifpga_rawdev/base/ifpga_api.c
index c447b3c..3ddbcdc 100644
--- a/drivers/raw/ifpga_rawdev/base/ifpga_api.c
+++ b/drivers/raw/ifpga_rawdev/base/ifpga_api.c
@@ -170,7 +170,6 @@  struct opae_accelerator_ops ifpga_acc_ops = {
 };
 
 /* Bridge APIs */
-
 static int ifpga_br_reset(struct opae_bridge *br)
 {
 	struct ifpga_port_hw *port = br->data;
@@ -192,8 +191,26 @@  static int ifpga_mgr_flash(struct opae_manager *mgr, int id, void *buf,
 	return ifpga_pr(hw, id, buf, size, status);
 }
 
+static int ifpga_mgr_get_eth_group_region_info(struct opae_manager *mgr,
+		struct opae_eth_group_region_info *info)
+{
+	struct ifpga_fme_hw *fme = mgr->data;
+
+	if (info->group_id >= MAX_ETH_GROUP_DEVICES)
+		return -EINVAL;
+
+	info->phys_addr = fme->eth_group_region[info->group_id].phys_addr;
+	info->addr = fme->eth_group_region[info->group_id].addr;
+	info->len = fme->eth_group_region[info->group_id].len;
+
+	info->mem_idx = fme->nums_acc_region + info->group_id;
+
+	return 0;
+}
+
 struct opae_manager_ops ifpga_mgr_ops = {
 	.flash = ifpga_mgr_flash,
+	.get_eth_group_region_info = ifpga_mgr_get_eth_group_region_info,
 };
 
 static int ifpga_mgr_read_mac_rom(struct opae_manager *mgr, int offset,
@@ -212,10 +229,65 @@  static int ifpga_mgr_write_mac_rom(struct opae_manager *mgr, int offset,
 	return fme_mgr_write_mac_rom(fme, offset, buf, size);
 }
 
+static int ifpga_mgr_get_eth_group_nums(struct opae_manager *mgr)
+{
+	struct ifpga_fme_hw *fme = mgr->data;
+
+	return fme_mgr_get_eth_group_nums(fme);
+}
+
+static int ifpga_mgr_get_eth_group_info(struct opae_manager *mgr,
+		u8 group_id, struct opae_eth_group_info *info)
+{
+	struct ifpga_fme_hw *fme = mgr->data;
+
+	return fme_mgr_get_eth_group_info(fme, group_id, info);
+}
+
+static int ifpga_mgr_eth_group_reg_read(struct opae_manager *mgr, u8 group_id,
+		u8 type, u8 index, u16 addr, u32 *data)
+{
+	struct ifpga_fme_hw *fme = mgr->data;
+
+	return fme_mgr_eth_group_read_reg(fme, group_id,
+			type, index, addr, data);
+}
+
+static int ifpga_mgr_eth_group_reg_write(struct opae_manager *mgr, u8 group_id,
+		u8 type, u8 index, u16 addr, u32 data)
+{
+	struct ifpga_fme_hw *fme = mgr->data;
+
+	return fme_mgr_eth_group_write_reg(fme, group_id,
+			type, index, addr, data);
+}
+
+static int ifpga_mgr_get_retimer_info(struct opae_manager *mgr,
+		struct opae_retimer_info *info)
+{
+	struct ifpga_fme_hw *fme = mgr->data;
+
+	return fme_mgr_get_retimer_info(fme, info);
+}
+
+static int ifpga_mgr_get_retimer_status(struct opae_manager *mgr,
+		struct opae_retimer_status *status)
+{
+	struct ifpga_fme_hw *fme = mgr->data;
+
+	return fme_mgr_get_retimer_status(fme, status);
+}
+
 /* Network APIs in FME */
 struct opae_manager_networking_ops ifpga_mgr_network_ops = {
 	.read_mac_rom = ifpga_mgr_read_mac_rom,
 	.write_mac_rom = ifpga_mgr_write_mac_rom,
+	.get_eth_group_nums = ifpga_mgr_get_eth_group_nums,
+	.get_eth_group_info = ifpga_mgr_get_eth_group_info,
+	.eth_group_reg_read = ifpga_mgr_eth_group_reg_read,
+	.eth_group_reg_write = ifpga_mgr_eth_group_reg_write,
+	.get_retimer_info = ifpga_mgr_get_retimer_info,
+	.get_retimer_status = ifpga_mgr_get_retimer_status,
 };
 
 /* Adapter APIs */
diff --git a/drivers/raw/ifpga_rawdev/base/ifpga_defines.h b/drivers/raw/ifpga_rawdev/base/ifpga_defines.h
index 62f71c7..b7151ca 100644
--- a/drivers/raw/ifpga_rawdev/base/ifpga_defines.h
+++ b/drivers/raw/ifpga_rawdev/base/ifpga_defines.h
@@ -22,6 +22,7 @@ 
 #define FME_FEATURE_MAX10_SPI       "fme_max10_spi"
 #define FME_FEATURE_NIOS_SPI        "fme_nios_spi"
 #define FME_FEATURE_I2C_MASTER      "fme_i2c_master"
+#define FME_FEATURE_ETH_GROUP       "fme_eth_group"
 
 #define PORT_FEATURE_HEADER         "port_hdr"
 #define PORT_FEATURE_UAFU           "port_uafu"
@@ -88,6 +89,7 @@  enum fpga_id_type {
 #define FME_FEATURE_ID_MAX10_SPI  0xe
 #define FME_FEATURE_ID_NIOS_SPI 0xd
 #define FME_FEATURE_ID_I2C_MASTER  0xf
+#define FME_FEATURE_ID_ETH_GROUP 0x10
 
 #define PORT_FEATURE_ID_HEADER FEATURE_ID_FIU_HEADER
 #define PORT_FEATURE_ID_ERROR 0x10
@@ -1661,5 +1663,42 @@  struct bts_header {
 	(((bts_hdr)->guid_h == GBS_GUID_H) &&		\
 	((bts_hdr)->guid_l == GBS_GUID_L))
 
+/* bitstream id definition */
+struct fme_bitstream_id {
+	union {
+		u64 id;
+		struct {
+			u64 hash:32;
+			u64 interface:4;
+			u64 reserved:12;
+			u64 debug:4;
+			u64 patch:4;
+			u64 minor:4;
+			u64 major:4;
+		};
+	};
+};
+
+enum board_interface {
+	VC_8_10G = 0,
+	VC_4_25G = 1,
+	VC_2_1_25 = 2,
+	VC_4_25G_2_25G = 3,
+	VC_2_2_25G = 4,
+};
+
+struct ifpga_fme_board_info {
+	enum board_interface type;
+	u32 build_hash;
+	u32 debug_version;
+	u32 patch_version;
+	u32 minor_version;
+	u32 major_version;
+	u32 nums_of_retimer;
+	u32 ports_per_retimer;
+	u32 nums_of_fvl;
+	u32 ports_per_fvl;
+};
+
 #pragma pack(pop)
 #endif /* _BASE_IFPGA_DEFINES_H_ */
diff --git a/drivers/raw/ifpga_rawdev/base/ifpga_enumerate.c b/drivers/raw/ifpga_rawdev/base/ifpga_enumerate.c
index 666dae1..44086c1 100644
--- a/drivers/raw/ifpga_rawdev/base/ifpga_enumerate.c
+++ b/drivers/raw/ifpga_rawdev/base/ifpga_enumerate.c
@@ -232,6 +232,7 @@  static int build_info_commit_dev(struct build_feature_devs_info *binfo)
 	struct opae_bridge *br;
 	struct opae_accelerator *acc;
 	struct ifpga_port_hw *port;
+	struct ifpga_fme_hw *fme;
 	struct feature *feature;
 
 	if (!binfo->fiu)
@@ -264,8 +265,13 @@  static int build_info_commit_dev(struct build_feature_devs_info *binfo)
 		}
 
 		acc->br = br;
+		if (hw->adapter->mgr)
+			acc->mgr = hw->adapter->mgr;
 		acc->index = br->id;
 
+		fme = &hw->fme;
+		fme->nums_acc_region = info->num_regions;
+
 		opae_adapter_add_acc(hw->adapter, acc);
 
 	} else if (binfo->current_type == FME_ID) {
diff --git a/drivers/raw/ifpga_rawdev/base/ifpga_feature_dev.c b/drivers/raw/ifpga_rawdev/base/ifpga_feature_dev.c
index 0454f80..5ebc449 100644
--- a/drivers/raw/ifpga_rawdev/base/ifpga_feature_dev.c
+++ b/drivers/raw/ifpga_rawdev/base/ifpga_feature_dev.c
@@ -203,6 +203,8 @@  int port_clear_error(struct ifpga_port_hw *port)
 	&fme_nios_spi_master_ops),},
 	{FEATURE_DRV(FME_FEATURE_ID_I2C_MASTER, FME_FEATURE_I2C_MASTER,
 	&fme_i2c_master_ops),},
+	{FEATURE_DRV(FME_FEATURE_ID_ETH_GROUP, FME_FEATURE_ETH_GROUP,
+	&fme_eth_group_ops),},
 	{0, NULL, NULL}, /* end of arrary */
 };
 
diff --git a/drivers/raw/ifpga_rawdev/base/ifpga_feature_dev.h b/drivers/raw/ifpga_rawdev/base/ifpga_feature_dev.h
index a398a98..3f63f5a 100644
--- a/drivers/raw/ifpga_rawdev/base/ifpga_feature_dev.h
+++ b/drivers/raw/ifpga_rawdev/base/ifpga_feature_dev.h
@@ -173,6 +173,7 @@  int do_pr(struct ifpga_hw *hw, u32 port_id, void *buffer, u32 size,
 extern struct feature_ops fme_emif_ops;
 extern struct feature_ops fme_spi_master_ops;
 extern struct feature_ops fme_i2c_master_ops;
+extern struct feature_ops fme_eth_group_ops;
 extern struct feature_ops fme_nios_spi_master_ops;
 
 int port_get_prop(struct ifpga_port_hw *port, struct feature_prop *prop);
@@ -204,4 +205,15 @@  int fme_mgr_read_mac_rom(struct ifpga_fme_hw *fme, int offset,
 		void *buf, int size);
 int fme_mgr_write_mac_rom(struct ifpga_fme_hw *fme, int offset,
 		void *buf, int size);
+int fme_mgr_get_eth_group_nums(struct ifpga_fme_hw *fme);
+int fme_mgr_get_eth_group_info(struct ifpga_fme_hw *fme,
+		u8 group_id, struct opae_eth_group_info *info);
+int fme_mgr_eth_group_read_reg(struct ifpga_fme_hw *fme, u8 group_id,
+		u8 type, u8 index, u16 addr, u32 *data);
+int fme_mgr_eth_group_write_reg(struct ifpga_fme_hw *fme, u8 group_id,
+		u8 type, u8 index, u16 addr, u32 data);
+int fme_mgr_get_retimer_info(struct ifpga_fme_hw *fme,
+		struct opae_retimer_info *info);
+int fme_mgr_get_retimer_status(struct ifpga_fme_hw *fme,
+		struct opae_retimer_status *status);
 #endif /* _IFPGA_FEATURE_DEV_H_ */
diff --git a/drivers/raw/ifpga_rawdev/base/ifpga_fme.c b/drivers/raw/ifpga_rawdev/base/ifpga_fme.c
index 95e022e..2cfb158 100644
--- a/drivers/raw/ifpga_rawdev/base/ifpga_fme.c
+++ b/drivers/raw/ifpga_rawdev/base/ifpga_fme.c
@@ -769,6 +769,90 @@  struct feature_ops fme_emif_ops = {
 	.uinit = fme_emif_uinit,
 };
 
+static const char *board_type_to_string(u32 type)
+{
+	switch (type) {
+	case VC_8_10G:
+		return "VC_8x10G";
+	case VC_4_25G:
+		return "VC_4x25G";
+	case VC_2_1_25:
+		return "VC_2x1x25G";
+	case VC_4_25G_2_25G:
+		return "VC_4x25G+2x25G";
+	case VC_2_2_25G:
+		return "VC_2x2x25G";
+	}
+
+	return "unknown";
+}
+
+static int board_type_to_info(u32 type,
+		struct ifpga_fme_board_info *info)
+{
+	switch (type) {
+	case VC_8_10G:
+		info->nums_of_retimer = 2;
+		info->ports_per_retimer = 4;
+		info->nums_of_fvl = 2;
+		info->ports_per_fvl = 4;
+		break;
+	case VC_4_25G:
+		info->nums_of_retimer = 1;
+		info->ports_per_retimer = 4;
+		info->nums_of_fvl = 2;
+		info->ports_per_fvl = 2;
+		break;
+	case VC_2_1_25:
+		info->nums_of_retimer = 2;
+		info->ports_per_retimer = 1;
+		info->nums_of_fvl = 1;
+		info->ports_per_fvl = 2;
+		break;
+	case VC_2_2_25G:
+		info->nums_of_retimer = 2;
+		info->ports_per_retimer = 2;
+		info->nums_of_fvl = 2;
+		info->ports_per_fvl = 2;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int fme_get_board_interface(struct ifpga_fme_hw *fme)
+{
+	struct fme_bitstream_id id;
+
+	if (fme_hdr_get_bitstream_id(fme, &id.id))
+		return -EINVAL;
+
+	fme->board_info.type = id.interface;
+	fme->board_info.build_hash = id.hash;
+	fme->board_info.debug_version = id.debug;
+	fme->board_info.major_version = id.major;
+	fme->board_info.minor_version = id.minor;
+
+	dev_info(fme, "board type: %s major_version:%u minor_version:%u build_hash:%u\n",
+			board_type_to_string(fme->board_info.type),
+			fme->board_info.major_version,
+			fme->board_info.minor_version,
+			fme->board_info.build_hash);
+
+	if (board_type_to_info(fme->board_info.type, &fme->board_info))
+		return -EINVAL;
+
+	dev_info(fme, "get board info: nums_retimers %d ports_per_retimer %d nums_fvl %d ports_per_fvl %d\n",
+			fme->board_info.nums_of_retimer,
+			fme->board_info.ports_per_retimer,
+			fme->board_info.nums_of_fvl,
+			fme->board_info.ports_per_fvl);
+
+	return 0;
+}
+
 static int spi_self_checking(void)
 {
 	u32 val;
@@ -935,6 +1019,8 @@  static int fme_nios_spi_init(struct feature *feature)
 		goto release_dev;
 	}
 
+	fme_get_board_interface(fme);
+
 	fme->max10_dev = max10;
 
 	/* SPI self test */
@@ -1027,6 +1113,45 @@  struct feature_ops fme_i2c_master_ops = {
 	.uinit = fme_i2c_uninit,
 };
 
+static int fme_eth_group_init(struct feature *feature)
+{
+	struct ifpga_fme_hw *fme = (struct ifpga_fme_hw *)feature->parent;
+	struct eth_group_device *dev;
+
+	dev = (struct eth_group_device *)eth_group_probe(feature->addr);
+	if (!dev)
+		return -ENODEV;
+
+	fme->eth_dev[dev->group_id] = dev;
+
+	fme->eth_group_region[dev->group_id].addr =
+		feature->addr;
+	fme->eth_group_region[dev->group_id].phys_addr =
+		feature->phys_addr;
+	fme->eth_group_region[dev->group_id].len =
+		feature->size;
+
+	fme->nums_eth_dev++;
+
+	dev_info(NULL, "FME PHY Group %d Init.\n", dev->group_id);
+	dev_info(NULL, "found %d eth group, addr %p phys_addr 0x%llx len %u\n",
+			dev->group_id, feature->addr,
+			(unsigned long long)feature->phys_addr,
+			feature->size);
+
+	return 0;
+}
+
+static void fme_eth_group_uinit(struct feature *feature)
+{
+	UNUSED(feature);
+}
+
+struct feature_ops fme_eth_group_ops = {
+	.init = fme_eth_group_init,
+	.uinit = fme_eth_group_uinit,
+};
+
 int fme_mgr_read_mac_rom(struct ifpga_fme_hw *fme, int offset,
 		void *buf, int size)
 {
@@ -1050,3 +1175,128 @@  int fme_mgr_write_mac_rom(struct ifpga_fme_hw *fme, int offset,
 
 	return at24_eeprom_write(dev, AT24512_SLAVE_ADDR, offset, buf, size);
 }
+
+static struct eth_group_device *get_eth_group_dev(struct ifpga_fme_hw *fme,
+		u8 group_id)
+{
+	struct eth_group_device *dev;
+
+	if (group_id > (MAX_ETH_GROUP_DEVICES - 1))
+		return NULL;
+
+	dev = (struct eth_group_device *)fme->eth_dev[group_id];
+	if (!dev)
+		return NULL;
+
+	if (dev->status != ETH_GROUP_DEV_ATTACHED)
+		return NULL;
+
+	return dev;
+}
+
+int fme_mgr_get_eth_group_nums(struct ifpga_fme_hw *fme)
+{
+	return fme->nums_eth_dev;
+}
+
+int fme_mgr_get_eth_group_info(struct ifpga_fme_hw *fme,
+		u8 group_id, struct opae_eth_group_info *info)
+{
+	struct eth_group_device *dev;
+
+	dev = get_eth_group_dev(fme, group_id);
+	if (!dev)
+		return -ENODEV;
+
+	info->group_id = group_id;
+	info->speed = dev->speed;
+	info->nums_of_mac = dev->mac_num;
+	info->nums_of_phy = dev->phy_num;
+
+	return 0;
+}
+
+int fme_mgr_eth_group_read_reg(struct ifpga_fme_hw *fme, u8 group_id,
+		u8 type, u8 index, u16 addr, u32 *data)
+{
+	struct eth_group_device *dev;
+
+	dev = get_eth_group_dev(fme, group_id);
+	if (!dev)
+		return -ENODEV;
+
+	return eth_group_read_reg(dev, type, index, addr, data);
+}
+
+int fme_mgr_eth_group_write_reg(struct ifpga_fme_hw *fme, u8 group_id,
+		u8 type, u8 index, u16 addr, u32 data)
+{
+	struct eth_group_device *dev;
+
+	dev = get_eth_group_dev(fme, group_id);
+	if (!dev)
+		return -ENODEV;
+
+	return eth_group_write_reg(dev, type, index, addr, data);
+}
+
+static int fme_get_eth_group_speed(struct ifpga_fme_hw *fme,
+		u8 group_id)
+{
+	struct eth_group_device *dev;
+
+	dev = get_eth_group_dev(fme, group_id);
+	if (!dev)
+		return -ENODEV;
+
+	return dev->speed;
+}
+
+int fme_mgr_get_retimer_info(struct ifpga_fme_hw *fme,
+		struct opae_retimer_info *info)
+{
+	struct intel_max10_device *dev;
+
+	dev = (struct intel_max10_device *)fme->max10_dev;
+	if (!dev)
+		return -ENODEV;
+
+	info->nums_retimer = fme->board_info.nums_of_retimer;
+	info->ports_per_retimer = fme->board_info.ports_per_retimer;
+	info->nums_fvl = fme->board_info.nums_of_fvl;
+	info->ports_per_fvl = fme->board_info.ports_per_fvl;
+
+	/* The speed of PKVL is identical the eth group's speed */
+	info->support_speed = fme_get_eth_group_speed(fme,
+			LINE_SIDE_GROUP_ID);
+
+	return 0;
+}
+
+int fme_mgr_get_retimer_status(struct ifpga_fme_hw *fme,
+		struct opae_retimer_status *status)
+{
+	struct intel_max10_device *dev;
+	unsigned int val;
+
+	dev = (struct intel_max10_device *)fme->max10_dev;
+	if (!dev)
+		return -ENODEV;
+
+	if (max10_reg_read(PKVL_LINK_STATUS, &val)) {
+		dev_err(dev, "%s: read pkvl status fail\n", __func__);
+		return -EINVAL;
+	}
+
+	/* The speed of PKVL is identical the eth group's speed */
+	status->speed = fme_get_eth_group_speed(fme,
+			LINE_SIDE_GROUP_ID);
+
+	status->line_link_bitmap = val;
+
+	dev_debug(dev, "get retimer status: speed:%d. line_link_bitmap:0x%x\n",
+			status->speed,
+			status->line_link_bitmap);
+
+	return 0;
+}
diff --git a/drivers/raw/ifpga_rawdev/base/ifpga_hw.h b/drivers/raw/ifpga_rawdev/base/ifpga_hw.h
index e296dd2..a428d69 100644
--- a/drivers/raw/ifpga_rawdev/base/ifpga_hw.h
+++ b/drivers/raw/ifpga_rawdev/base/ifpga_hw.h
@@ -7,6 +7,7 @@ 
 
 #include "ifpga_defines.h"
 #include "opae_ifpga_hw_api.h"
+#include "opae_eth_group.h"
 
 /** List of private feateues */
 TAILQ_HEAD(ifpga_feature_list, feature);
@@ -82,6 +83,12 @@  struct ifpga_fme_hw {
 
 	void *max10_dev; /* MAX10 device */
 	void *i2c_master; /* I2C Master device */
+	void *eth_dev[MAX_ETH_GROUP_DEVICES];
+	struct opae_reg_region
+		eth_group_region[MAX_ETH_GROUP_DEVICES];
+	struct ifpga_fme_board_info board_info;
+	int nums_eth_dev;
+	unsigned int nums_acc_region;
 };
 
 enum ifpga_port_state {
diff --git a/drivers/raw/ifpga_rawdev/base/meson.build b/drivers/raw/ifpga_rawdev/base/meson.build
index 7655985..f1015bb 100644
--- a/drivers/raw/ifpga_rawdev/base/meson.build
+++ b/drivers/raw/ifpga_rawdev/base/meson.build
@@ -20,6 +20,7 @@  sources = [
 	'opae_intel_max10.c',
 	'opae_i2c.c',
 	'opae_at24_eeprom.c',
+	'opae_eth_group.c',
 ]
 
 error_cflags = ['-Wno-sign-compare', '-Wno-unused-value',
diff --git a/drivers/raw/ifpga_rawdev/base/opae_eth_group.c b/drivers/raw/ifpga_rawdev/base/opae_eth_group.c
new file mode 100644
index 0000000..8db6693
--- /dev/null
+++ b/drivers/raw/ifpga_rawdev/base/opae_eth_group.c
@@ -0,0 +1,145 @@ 
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2010-2019 Intel Corporation
+ */
+
+#include "opae_osdep.h"
+#include "opae_eth_group.h"
+
+#define DATA_VAL_INVL		1 /* us */
+#define DATA_VAL_POLL_TIMEOUT	10 /* us */
+
+static const char *eth_type_to_string(u8 type)
+{
+	switch (type) {
+	case ETH_GROUP_PHY:
+		return "phy";
+	case ETH_GROUP_MAC:
+		return "mac";
+	case ETH_GROUP_ETHER:
+		return "ethernet wrapper";
+	}
+
+	return "unknown";
+}
+
+static int eth_group_get_select(struct eth_group_device *dev,
+		u8 type, u8 index, u8 *select)
+{
+	/*
+	 * in different speed configuration, the index of
+	 * PHY and MAC are different.
+	 *
+	 * 1 ethernet wrapper -> Device Select 0x0 - fixed value
+	 * n PHYs             -> Device Select 0x2,4,6,8,A,C,E,10,...
+	 * n MACs             -> Device Select 0x3,5,7,9,B,D,F,11,...
+	 */
+
+	if (type == ETH_GROUP_PHY && index < dev->phy_num)
+		*select = index * 2 + 2;
+	else if (type == ETH_GROUP_MAC && index < dev->mac_num)
+		*select = index * 2 + 3;
+	else if (type == ETH_GROUP_ETHER && index == 0)
+		*select = 0;
+	else
+		return -EINVAL;
+
+	return 0;
+}
+
+int eth_group_write_reg(struct eth_group_device *dev,
+		u8 type, u8 index, u16 addr, u32 data)
+{
+	u8 dev_select = 0;
+	u64 v = 0;
+	int ret;
+
+	dev_debug(dev, "%s type %s index %u addr 0x%x\n",
+			__func__, eth_type_to_string(type), index, addr);
+
+	/* find device select */
+	ret = eth_group_get_select(dev, type, index, &dev_select);
+	if (ret)
+		return ret;
+
+	v = CMD_WR << CTRL_CMD_SHIT |
+		(u64)dev_select << CTRL_DS_SHIFT |
+		(u64)addr << CTRL_ADDR_SHIFT |
+		(data & CTRL_WR_DATA);
+
+	/* only PHY has additional feature bit */
+	if (type == ETH_GROUP_PHY)
+		v |= CTRL_FEAT_SELECT;
+
+	opae_writeq(v, dev->base + ETH_GROUP_CTRL);
+
+	return 0;
+}
+
+int eth_group_read_reg(struct eth_group_device *dev,
+		u8 type, u8 index, u16 addr, u32 *data)
+{
+	u8 dev_select = 0;
+	u64 v = 0;
+	int ret;
+
+	dev_debug(dev, "%s type %s index %u addr 0x%x\n",
+			__func__, eth_type_to_string(type), index,
+			addr);
+
+	/* find device select */
+	ret = eth_group_get_select(dev, type, index, &dev_select);
+	if (ret)
+		return ret;
+
+	v = CMD_RD << CTRL_CMD_SHIT |
+		(u64)dev_select << CTRL_DS_SHIFT |
+		(u64)addr << CTRL_ADDR_SHIFT;
+
+	/* only PHY has additional feature bit */
+	if (type == ETH_GROUP_PHY)
+		v |= CTRL_FEAT_SELECT;
+
+	opae_writeq(v, dev->base + ETH_GROUP_CTRL);
+
+	if (opae_readq_poll_timeout(dev->base + ETH_GROUP_STAT,
+			v, v & STAT_DATA_VAL, DATA_VAL_INVL,
+			DATA_VAL_POLL_TIMEOUT))
+		return -ETIMEDOUT;
+
+	*data = (v & STAT_RD_DATA);
+
+	dev_debug(dev, "%s data 0x%x\n", __func__, *data);
+
+	return 0;
+}
+
+struct eth_group_device *eth_group_probe(void *base)
+{
+	struct eth_group_device *dev;
+
+	dev = opae_malloc(sizeof(*dev));
+	if (!dev)
+		return NULL;
+
+	dev->base = (u8 *)base;
+
+	dev->info.info = opae_readq(dev->base + ETH_GROUP_INFO);
+	dev->group_id = dev->info.group_id;
+	dev->phy_num = dev->mac_num = dev->info.num_phys;
+	dev->speed = dev->info.speed;
+
+	dev->status = ETH_GROUP_DEV_ATTACHED;
+
+	dev_info(dev, "eth group device %d probe done: phy_num=mac_num:%d, speed=%d\n",
+			dev->group_id, dev->phy_num, dev->speed);
+
+	return dev;
+}
+
+void eth_group_release(struct eth_group_device *dev)
+{
+	if (dev) {
+		dev->status = ETH_GROUP_DEV_NOUSED;
+		opae_free(dev);
+	}
+}
diff --git a/drivers/raw/ifpga_rawdev/base/opae_eth_group.h b/drivers/raw/ifpga_rawdev/base/opae_eth_group.h
new file mode 100644
index 0000000..8d695cc
--- /dev/null
+++ b/drivers/raw/ifpga_rawdev/base/opae_eth_group.h
@@ -0,0 +1,96 @@ 
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2010-2019 Intel Corporation
+ */
+
+#ifndef _OPAE_PHY_MAC_H
+#define _OPAE_PHY_MAC_H
+
+#include "opae_osdep.h"
+
+#define MAX_ETH_GROUP_DEVICES 2
+
+#define LINE_SIDE_GROUP_ID 0
+#define HOST_SIDE_GROUP_ID 1
+
+#define ETH_GROUP_SELECT_FEAT 1
+
+#define ETH_GROUP_PHY 1
+#define ETH_GROUP_MAC 2
+#define ETH_GROUP_ETHER 3
+
+#define ETH_GROUP_INFO		0x8
+#define INFO_SPEED		GENMASK_ULL(23, 16)
+#define ETH_SPEED_10G		10
+#define ETH_SPEED_25G		25
+#define INFO_PHY_NUM		GENMASK_ULL(15, 8)
+#define INFO_GROUP_NUM		GENMASK_ULL(7, 0)
+
+#define ETH_GROUP_CTRL		0x10
+#define CTRL_CMD		GENMASK_ULL(63, 62)
+#define CTRL_CMD_SHIT           62
+#define CMD_NOP			0ULL
+#define CMD_RD			1ULL
+#define CMD_WR			2ULL
+#define CTRL_DEV_SELECT		GENMASK_ULL(52, 49)
+#define CTRL_DS_SHIFT   49
+#define CTRL_FEAT_SELECT	BIT_ULL(48)
+#define SELECT_IP		0
+#define SELECT_FEAT		1
+#define CTRL_ADDR		GENMASK_ULL(47, 32)
+#define CTRL_ADDR_SHIFT         32
+#define CTRL_WR_DATA		GENMASK_ULL(31, 0)
+
+#define ETH_GROUP_STAT		0x18
+#define STAT_DATA_VAL		BIT_ULL(32)
+#define STAT_RD_DATA		GENMASK_ULL(31, 0)
+
+struct opae_eth_group_info {
+	u8 group_id;
+	u8 speed;
+	u8 nums_of_phy;
+	u8 nums_of_mac;
+};
+
+struct opae_eth_group_region_info {
+	u8 group_id;
+	u64 phys_addr;
+	u64 len;
+	u8 *addr;
+	u8 mem_idx;
+};
+
+struct eth_group_info_reg {
+	union {
+		u64 info;
+		struct {
+			u8 group_id:8;
+			u8 num_phys:8;
+			u8 speed:8;
+			u8 direction:1;
+			u64 resvd:39;
+		};
+	};
+};
+
+enum eth_group_status {
+	ETH_GROUP_DEV_NOUSED = 0,
+	ETH_GROUP_DEV_ATTACHED,
+};
+
+struct eth_group_device {
+	u8 *base;
+	struct eth_group_info_reg info;
+	enum eth_group_status status;
+	u8 speed;
+	u8 group_id;
+	u8 phy_num;
+	u8 mac_num;
+};
+
+struct eth_group_device *eth_group_probe(void *base);
+void eth_group_release(struct eth_group_device *dev);
+int eth_group_read_reg(struct eth_group_device *dev,
+		u8 type, u8 index, u16 addr, u32 *data);
+int eth_group_write_reg(struct eth_group_device *dev,
+		u8 type, u8 index, u16 addr, u32 data);
+#endif
diff --git a/drivers/raw/ifpga_rawdev/base/opae_hw_api.c b/drivers/raw/ifpga_rawdev/base/opae_hw_api.c
index ec2b4c7..0e117d0 100644
--- a/drivers/raw/ifpga_rawdev/base/opae_hw_api.c
+++ b/drivers/raw/ifpga_rawdev/base/opae_hw_api.c
@@ -426,3 +426,152 @@  int opae_manager_write_mac_rom(struct opae_manager *mgr, int port,
 
 	return -ENOENT;
 }
+
+/**
+ * opae_manager_get_eth_group_nums - get eth group numbers
+ * @mgr: opae_manager for eth group
+ *
+ * Return: the numbers of eth group
+ */
+int opae_manager_get_eth_group_nums(struct opae_manager *mgr)
+{
+	if (!mgr || !mgr->network_ops)
+		return -EINVAL;
+
+	if (mgr->network_ops->get_retimer_info)
+		return mgr->network_ops->get_eth_group_nums(mgr);
+
+	return -ENOENT;
+}
+
+/**
+ * opae_manager_get_eth_group_info - get eth group info
+ * @mgr: opae_manager for eth group
+ * @group_id: id for eth group
+ * @info: info return to caller
+ *
+ * Return: 0 on success, otherwise error code
+ */
+int opae_manager_get_eth_group_info(struct opae_manager *mgr,
+	       u8 group_id, struct opae_eth_group_info *info)
+{
+	if (!mgr || !mgr->network_ops)
+		return -EINVAL;
+
+	if (mgr->network_ops->get_retimer_info)
+		return mgr->network_ops->get_eth_group_info(mgr,
+			group_id, info);
+
+	return -ENOENT;
+}
+
+/**
+ * opae_manager_get_eth_group_region_info
+ * @mgr: opae_manager for flash.
+ * @info: the memory region info for eth group
+ *
+ * Return: 0 on success, otherwise error code.
+ */
+int opae_manager_get_eth_group_region_info(struct opae_manager *mgr,
+		u8 group_id, struct opae_eth_group_region_info *info)
+{
+	if (!mgr)
+		return -EINVAL;
+
+	if (group_id >= MAX_ETH_GROUP_DEVICES)
+		return -EINVAL;
+
+	info->group_id = group_id;
+
+	if (mgr && mgr->ops && mgr->ops->get_eth_group_region_info)
+		return mgr->ops->get_eth_group_region_info(mgr, info);
+
+	return -ENOENT;
+}
+
+/**
+ * opae_manager_eth_group_read_reg - read ETH group register
+ * @mgr: opae_manager for ETH Group
+ * @group_id: ETH group id
+ * @type: eth type
+ * @index: port index in eth group device
+ * @addr: register address of ETH Group
+ * @data: read buffer
+ *
+ * Return: 0 on success, otherwise error code
+ */
+int opae_manager_eth_group_read_reg(struct opae_manager *mgr, u8 group_id,
+		u8 type, u8 index, u16 addr, u32 *data)
+{
+	if (!mgr || !mgr->network_ops)
+		return -EINVAL;
+
+	if (mgr->network_ops->eth_group_reg_read)
+		return mgr->network_ops->eth_group_reg_read(mgr, group_id,
+				type, index, addr, data);
+
+	return -ENOENT;
+}
+
+/**
+ * opae_manager_eth_group_write_reg - write ETH group register
+ * @mgr: opae_manager for ETH Group
+ * @group_id: ETH group id
+ * @type: eth type
+ * @index: port index in eth group device
+ * @addr: register address of ETH Group
+ * @data: data will write to register
+ *
+ * Return: 0 on success, otherwise error code
+ */
+int opae_manager_eth_group_write_reg(struct opae_manager *mgr, u8 group_id,
+		u8 type, u8 index, u16 addr, u32 data)
+{
+	if (!mgr || !mgr->network_ops)
+		return -EINVAL;
+
+	if (mgr->network_ops->eth_group_reg_write)
+		return mgr->network_ops->eth_group_reg_write(mgr, group_id,
+				type, index, addr, data);
+
+	return -ENOENT;
+}
+
+/**
+ * opae_manager_get_retimer_info - get retimer info like PKVL chip
+ * @mgr: opae_manager for retimer
+ * @info: info return to caller
+ *
+ * Return: 0 on success, otherwise error code
+ */
+int opae_manager_get_retimer_info(struct opae_manager *mgr,
+	       struct opae_retimer_info *info)
+{
+	if (!mgr || !mgr->network_ops)
+		return -EINVAL;
+
+	if (mgr->network_ops->get_retimer_info)
+		return mgr->network_ops->get_retimer_info(mgr, info);
+
+	return -ENOENT;
+}
+
+/**
+ * opae_manager_get_retimer_status - get retimer status
+ * @mgr: opae_manager of retimer
+ * @status: status of retimer
+ *
+ * Return: 0 on success, otherwise error code
+ */
+int opae_manager_get_retimer_status(struct opae_manager *mgr,
+		struct opae_retimer_status *status)
+{
+	if (!mgr || !mgr->network_ops)
+		return -EINVAL;
+
+	if (mgr->network_ops->get_retimer_status)
+		return mgr->network_ops->get_retimer_status(mgr,
+				status);
+
+	return -ENOENT;
+}
diff --git a/drivers/raw/ifpga_rawdev/base/opae_hw_api.h b/drivers/raw/ifpga_rawdev/base/opae_hw_api.h
index 826da37..383e751 100644
--- a/drivers/raw/ifpga_rawdev/base/opae_hw_api.h
+++ b/drivers/raw/ifpga_rawdev/base/opae_hw_api.h
@@ -12,6 +12,7 @@ 
 
 #include "opae_osdep.h"
 #include "opae_intel_max10.h"
+#include "opae_eth_group.h"
 
 #ifndef PCI_MAX_RESOURCE
 #define PCI_MAX_RESOURCE 6
@@ -45,6 +46,8 @@  struct opae_manager {
 struct opae_manager_ops {
 	int (*flash)(struct opae_manager *mgr, int id, void *buffer,
 		     u32 size, u64 *status);
+	int (*get_eth_group_region_info)(struct opae_manager *mgr,
+			struct opae_eth_group_region_info *info);
 };
 
 /* networking management ops in FME */
@@ -53,6 +56,17 @@  struct opae_manager_networking_ops {
 			int size);
 	int (*write_mac_rom)(struct opae_manager *mgr, int offset, void *buf,
 			int size);
+	int (*get_eth_group_nums)(struct opae_manager *mgr);
+	int (*get_eth_group_info)(struct opae_manager *mgr,
+			u8 group_id, struct opae_eth_group_info *info);
+	int (*eth_group_reg_read)(struct opae_manager *mgr, u8 group_id,
+			u8 type, u8 index, u16 addr, u32 *data);
+	int (*eth_group_reg_write)(struct opae_manager *mgr, u8 group_id,
+			u8 type, u8 index, u16 addr, u32 data);
+	int (*get_retimer_info)(struct opae_manager *mgr,
+			struct opae_retimer_info *info);
+	int (*get_retimer_status)(struct opae_manager *mgr,
+			struct opae_retimer_status *status);
 };
 
 /* OPAE Manager APIs */
@@ -62,6 +76,8 @@  struct opae_manager *
 #define opae_manager_free(mgr) opae_free(mgr)
 int opae_manager_flash(struct opae_manager *mgr, int acc_id, void *buf,
 		       u32 size, u64 *status);
+int opae_manager_get_eth_group_region_info(struct opae_manager *mgr,
+		u8 group_id, struct opae_eth_group_region_info *info);
 
 /* OPAE Bridge Data Structure */
 struct opae_bridge_ops;
@@ -276,4 +292,15 @@  int opae_manager_read_mac_rom(struct opae_manager *mgr, int port,
 		struct opae_ether_addr *addr);
 int opae_manager_write_mac_rom(struct opae_manager *mgr, int port,
 		struct opae_ether_addr *addr);
+int opae_manager_get_retimer_info(struct opae_manager *mgr,
+		struct opae_retimer_info *info);
+int opae_manager_get_retimer_status(struct opae_manager *mgr,
+		struct opae_retimer_status *status);
+int opae_manager_get_eth_group_nums(struct opae_manager *mgr);
+int opae_manager_get_eth_group_info(struct opae_manager *mgr,
+		u8 group_id, struct opae_eth_group_info *info);
+int opae_manager_eth_group_write_reg(struct opae_manager *mgr, u8 group_id,
+		u8 type, u8 index, u16 addr, u32 data);
+int opae_manager_eth_group_read_reg(struct opae_manager *mgr, u8 group_id,
+		u8 type, u8 index, u16 addr, u32 *data);
 #endif /* _OPAE_HW_API_H_*/
diff --git a/drivers/raw/ifpga_rawdev/base/opae_intel_max10.h b/drivers/raw/ifpga_rawdev/base/opae_intel_max10.h
index 91a188d..08b387e 100644
--- a/drivers/raw/ifpga_rawdev/base/opae_intel_max10.h
+++ b/drivers/raw/ifpga_rawdev/base/opae_intel_max10.h
@@ -8,9 +8,6 @@ 
 #include "opae_osdep.h"
 #include "opae_spi.h"
 
-#define INTEL_MAX10_MAX_MDIO_DEVS 2
-#define PKVL_NUMBER_PORTS  4
-
 /* max10 capability flags */
 #define MAX10_FLAGS_NO_I2C2		BIT(0)
 #define MAX10_FLAGS_NO_BMCIMG_FLASH	BIT(1)
@@ -25,6 +22,45 @@  struct intel_max10_device {
 	struct spi_transaction_dev *spi_tran_dev;
 };
 
+/* retimer speed */
+enum retimer_speed {
+	MXD_1GB = 1,
+	MXD_2_5GB = 2,
+	MXD_5GB = 5,
+	MXD_10GB = 10,
+	MXD_25GB = 25,
+	MXD_40GB = 40,
+	MXD_100GB = 100,
+	MXD_SPEED_UNKNOWN,
+};
+
+/* retimer info */
+struct opae_retimer_info {
+	unsigned int nums_retimer;
+	unsigned int ports_per_retimer;
+	unsigned int nums_fvl;
+	unsigned int ports_per_fvl;
+	enum retimer_speed support_speed;
+};
+
+/* retimer status*/
+struct opae_retimer_status {
+	enum retimer_speed speed;
+	/*
+	 * retimer line link status bitmap:
+	 * bit 0: Retimer0 Port0 link status
+	 * bit 1: Retimer0 Port1 link status
+	 * bit 2: Retimer0 Port2 link status
+	 * bit 3: Retimer0 Port3 link status
+	 *
+	 * bit 4: Retimer1 Port0 link status
+	 * bit 5: Retimer1 Port1 link status
+	 * bit 6: Retimer1 Port2 link status
+	 * bit 7: Retimer1 Port3 link status
+	 */
+	unsigned int line_link_bitmap;
+};
+
 #define FLASH_BASE 0x10000000
 #define FLASH_OPTION_BITS 0x10000
 
diff --git a/drivers/raw/ifpga_rawdev/base/opae_osdep.h b/drivers/raw/ifpga_rawdev/base/opae_osdep.h
index d710ec0..1596adc 100644
--- a/drivers/raw/ifpga_rawdev/base/opae_osdep.h
+++ b/drivers/raw/ifpga_rawdev/base/opae_osdep.h
@@ -53,12 +53,7 @@  struct uuid {
 #define dev_err(x, args...) dev_printf(ERR, args)
 #define dev_info(x, args...) dev_printf(INFO, args)
 #define dev_warn(x, args...) dev_printf(WARNING, args)
-
-#ifdef OPAE_DEBUG
 #define dev_debug(x, args...) dev_printf(DEBUG, args)
-#else
-#define dev_debug(x, args...) do { } while (0)
-#endif
 
 #define pr_err(y, args...) dev_err(0, y, ##args)
 #define pr_warn(y, args...) dev_warn(0, y, ##args)
@@ -81,4 +76,15 @@  struct uuid {
 #define time_before(a, b)	time_after(b, a)
 #define opae_memset(a, b, c)    memset((a), (b), (c))
 
+#define opae_readq_poll_timeout(addr, val, cond, invl, timeout)\
+({									     \
+	int wait = 0;							     \
+	for (; wait <= timeout; wait += invl) {			     \
+		(val) = opae_readq(addr);				     \
+		if (cond)                  \
+			break;						     \
+		udelay(invl);						     \
+	}								     \
+	(cond) ? 0 : -ETIMEDOUT;	  \
+})
 #endif