From patchwork Wed Mar 27 11:53:37 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akhil Goyal X-Patchwork-Id: 51798 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 6E3B21B3B5; Wed, 27 Mar 2019 12:53:50 +0100 (CET) Received: from EUR01-VE1-obe.outbound.protection.outlook.com (mail-eopbgr140070.outbound.protection.outlook.com [40.107.14.70]) by dpdk.org (Postfix) with ESMTP id 3B7481B209 for ; Wed, 27 Mar 2019 12:53:38 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=6hEMOSb9bDgvMlBYJxSscfyVJAjsOdOJXerBSKzX0rg=; b=En04LLwIgwsGBRIl54oe4KyuJ1N1lhCWlneld1o1eqgt9a/agYCpEaIGCRIOHBFfnXD3smTLPuYu8qoAtSNHsJ1RFjZ6kGSZdGtGjsR0PUMKelchncbFhYRF6GRAVH+LQIUR/KI3UOz5AFU3AciRrXx/187ITELpZF7zSm5aTi8= Received: from VI1PR04MB4893.eurprd04.prod.outlook.com (20.177.49.154) by VI1PR04MB3261.eurprd04.prod.outlook.com (10.170.231.138) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1730.19; 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DIR:OUT; SFP:1101; SCL:1; SRVR:VI1PR04MB3261; H:VI1PR04MB4893.eurprd04.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: XSR4u6i9Sh98eRCU5Zy8OjZRsRkH5Zrqqsv1cOKiL9M1+ZiAo6mKd3LQ0i1SAeadupgVwjZTpYdFqYwklbnGgx9cT2lkxq9og4k0ekDbz7u8S9h5Ns8d80N5snSAiy31J2Seq84uo7UFni7MuiGUaATpevJWTDoY1L3qa+D4kRR39FdJhHDkzl1GesrDAA9vp9wMb0lEfrnhy3qMr681W5DNpNSvJ13o8SVhnsBc5yMMcOb7U29nxEUmG524vCt8NHqRXNwyx2Bph4JQiiiCVEQqlhgbu076zBwulb0r9rjNvHwLRG/eHcTxtQgSEvFsD71fIEjsfTAsHqV7BXUaxxu9/y8YPFMOu7x/e0Y6fpfFPsSUuCdy+o84hrH85nR8LH2zrdCJ19/hmqLGxLQAu3sN1Hstl/AJuFoZ7pu8dcc= MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 7fc7d817-d5e4-46fe-5772-08d6b2aad8ba X-MS-Exchange-CrossTenant-originalarrivaltime: 27 Mar 2019 11:53:37.2430 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR04MB3261 Subject: [dpdk-dev] [PATCH 6/6] crypto/dpaa2_sec: support multi process X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" - fle pool allocations should be done for each process. - cryptodev->data is shared across muliple processes but cryptodev itself is allocated for each process. So any information which needs to be shared between processes, should be kept in cryptodev->data. Signed-off-by: Akhil Goyal --- drivers/bus/fslmc/portal/dpaa2_hw_pvt.h | 2 +- drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c | 26 ++++++++++----------- 2 files changed, 13 insertions(+), 15 deletions(-) diff --git a/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h b/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h index 4679e9340..0cbde8a9b 100644 --- a/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h +++ b/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h @@ -152,7 +152,7 @@ struct dpaa2_queue { struct rte_mempool *mb_pool; /**< mbuf pool to populate RX ring. */ union { struct rte_eth_dev_data *eth_data; - void *dev; + struct rte_cryptodev_data *crypto_data; }; int32_t eventfd; /*!< Event Fd of this queue */ uint32_t fqid; /*!< Unique ID of this queue */ diff --git a/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c b/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c index 31b7de679..5b72b9ee4 100644 --- a/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c +++ b/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c @@ -7,6 +7,7 @@ #include #include +#include #include #include @@ -1297,7 +1298,7 @@ dpaa2_sec_enqueue_burst(void *qp, struct rte_crypto_op **ops, } static inline struct rte_crypto_op * -sec_simple_fd_to_mbuf(const struct qbman_fd *fd, __rte_unused uint8_t id) +sec_simple_fd_to_mbuf(const struct qbman_fd *fd) { struct rte_crypto_op *op; uint16_t len = DPAA2_GET_FD_LEN(fd); @@ -1326,7 +1327,7 @@ sec_simple_fd_to_mbuf(const struct qbman_fd *fd, __rte_unused uint8_t id) } static inline struct rte_crypto_op * -sec_fd_to_mbuf(const struct qbman_fd *fd, uint8_t driver_id) +sec_fd_to_mbuf(const struct qbman_fd *fd) { struct qbman_fle *fle; struct rte_crypto_op *op; @@ -1334,7 +1335,7 @@ sec_fd_to_mbuf(const struct qbman_fd *fd, uint8_t driver_id) struct rte_mbuf *dst, *src; if (DPAA2_FD_GET_FORMAT(fd) == qbman_fd_single) - return sec_simple_fd_to_mbuf(fd, driver_id); + return sec_simple_fd_to_mbuf(fd); fle = (struct qbman_fle *)DPAA2_IOVA_TO_VADDR(DPAA2_GET_FD_ADDR(fd)); @@ -1401,8 +1402,6 @@ dpaa2_sec_dequeue_burst(void *qp, struct rte_crypto_op **ops, { /* Function is responsible to receive frames for a given device and VQ*/ struct dpaa2_sec_qp *dpaa2_qp = (struct dpaa2_sec_qp *)qp; - struct rte_cryptodev *dev = - (struct rte_cryptodev *)(dpaa2_qp->rx_vq.dev); struct qbman_result *dq_storage; uint32_t fqid = dpaa2_qp->rx_vq.fqid; int ret, num_rx = 0; @@ -1472,7 +1471,7 @@ dpaa2_sec_dequeue_burst(void *qp, struct rte_crypto_op **ops, } fd = qbman_result_DQ_fd(dq_storage); - ops[num_rx] = sec_fd_to_mbuf(fd, dev->driver_id); + ops[num_rx] = sec_fd_to_mbuf(fd); if (unlikely(fd->simple.frc)) { /* TODO Parse SEC errors */ @@ -1546,8 +1545,8 @@ dpaa2_sec_queue_pair_setup(struct rte_cryptodev *dev, uint16_t qp_id, return -1; } - qp->rx_vq.dev = dev; - qp->tx_vq.dev = dev; + qp->rx_vq.crypto_data = dev->data; + qp->tx_vq.crypto_data = dev->data; qp->rx_vq.q_storage = rte_malloc("sec dq storage", sizeof(struct queue_storage_info_t), RTE_CACHE_LINE_SIZE); @@ -3116,8 +3115,7 @@ dpaa2_sec_process_parallel_event(struct qbman_swp *swp, ev->sched_type = rxq->ev.sched_type; ev->queue_id = rxq->ev.queue_id; ev->priority = rxq->ev.priority; - ev->event_ptr = sec_fd_to_mbuf(fd, ((struct rte_cryptodev *) - (rxq->dev))->driver_id); + ev->event_ptr = sec_fd_to_mbuf(fd); qbman_swp_dqrr_consume(swp, dq); } @@ -3145,8 +3143,7 @@ dpaa2_sec_process_atomic_event(struct qbman_swp *swp __attribute__((unused)), ev->queue_id = rxq->ev.queue_id; ev->priority = rxq->ev.priority; - ev->event_ptr = sec_fd_to_mbuf(fd, ((struct rte_cryptodev *) - (rxq->dev))->driver_id); + ev->event_ptr = sec_fd_to_mbuf(fd); dqrr_index = qbman_get_dqrr_idx(dq); crypto_op->sym->m_src->seqn = dqrr_index + 1; DPAA2_PER_LCORE_DQRR_SIZE++; @@ -3275,7 +3272,7 @@ dpaa2_sec_dev_init(struct rte_cryptodev *cryptodev) uint16_t token; struct dpseci_attr attr; int retcode, hw_id; - char str[20]; + char str[30]; PMD_INIT_FUNC_TRACE(); dpaa2_dev = container_of(dev, struct rte_dpaa2_device, device); @@ -3353,7 +3350,8 @@ dpaa2_sec_dev_init(struct rte_cryptodev *cryptodev) internals->hw = dpseci; internals->token = token; - snprintf(str, sizeof(str), "fle_pool_%d", cryptodev->data->dev_id); + snprintf(str, sizeof(str), "sec_fle_pool_p%d_%d", + getpid(), cryptodev->data->dev_id); internals->fle_pool = rte_mempool_create((const char *)str, FLE_POOL_NUM_BUFS, FLE_POOL_BUF_SIZE,