[v6,2/4] meson: add infra to support machine specific flags

Message ID 20190318164949.2357-2-jerinj@marvell.com
State Superseded, archived
Delegated to: Thomas Monjalon
Headers show
Series
  • [v6,1/4] mk: introduce helper to check valid compiler argument
Related show

Checks

Context Check Description
ci/Intel-compilation success Compilation OK
ci/checkpatch success coding style OK

Commit Message

Jerin Jacob Kollanukkaran March 18, 2019, 4:50 p.m.
From: Pavan Nikhilesh <pbhagavatula@marvell.com>

Currently, RTE_* flags are set based on the implementer ID but there might
be some micro arch specific differences from the same vendor
eg. CACHE_LINESIZE. Add support to set micro arch specific flags.

Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Signed-off-by: Jerin Jacob <jerinj@marvell.com>
---
 config/arm/meson.build | 37 ++++++++++++++++++++++++++++++++-----
 1 file changed, 32 insertions(+), 5 deletions(-)

Comments

Bruce Richardson March 19, 2019, 9:40 a.m. | #1
On Mon, Mar 18, 2019 at 04:50:16PM +0000, Jerin Jacob Kollanukkaran wrote:
> From: Pavan Nikhilesh <pbhagavatula@marvell.com>
> 
> Currently, RTE_* flags are set based on the implementer ID but there might
> be some micro arch specific differences from the same vendor
> eg. CACHE_LINESIZE. Add support to set micro arch specific flags.
> 
> Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
> Signed-off-by: Jerin Jacob <jerinj@marvell.com>
> ---
>  config/arm/meson.build | 37 ++++++++++++++++++++++++++++++++-----
>  1 file changed, 32 insertions(+), 5 deletions(-)
> 
This looks ok to me, but I think review and ack from another Arm vendor
would be good to have.

/Bruce
Thomas Monjalon March 29, 2019, 1:57 p.m. | #2
19/03/2019 10:40, Bruce Richardson:
> On Mon, Mar 18, 2019 at 04:50:16PM +0000, Jerin Jacob Kollanukkaran wrote:
> > From: Pavan Nikhilesh <pbhagavatula@marvell.com>
> > 
> > Currently, RTE_* flags are set based on the implementer ID but there might
> > be some micro arch specific differences from the same vendor
> > eg. CACHE_LINESIZE. Add support to set micro arch specific flags.
> > 
> > Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
> > Signed-off-by: Jerin Jacob <jerinj@marvell.com>
> > ---
> >  config/arm/meson.build | 37 ++++++++++++++++++++++++++++++++-----
> >  1 file changed, 32 insertions(+), 5 deletions(-)
> > 
> This looks ok to me, but I think review and ack from another Arm vendor
> would be good to have.

Adding Cc's for more reviews

Patch

diff --git a/config/arm/meson.build b/config/arm/meson.build
index 8e892fa77..3db6d6445 100644
--- a/config/arm/meson.build
+++ b/config/arm/meson.build
@@ -52,12 +52,10 @@  flags_generic = [
 	['RTE_USE_C11_MEM_MODEL', true],
 	['RTE_CACHE_LINE_SIZE', 128]]
 flags_cavium = [
-	['RTE_MACHINE', '"thunderx"'],
 	['RTE_CACHE_LINE_SIZE', 128],
 	['RTE_MAX_NUMA_NODES', 2],
 	['RTE_MAX_LCORE', 96],
-	['RTE_MAX_VFIO_GROUPS', 128],
-	['RTE_USE_C11_MEM_MODEL', false]]
+	['RTE_MAX_VFIO_GROUPS', 128]]
 flags_dpaa = [
 	['RTE_MACHINE', '"dpaa"'],
 	['RTE_USE_C11_MEM_MODEL', true],
@@ -71,6 +69,27 @@  flags_dpaa2 = [
 	['RTE_MAX_NUMA_NODES', 1],
 	['RTE_MAX_LCORE', 16],
 	['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false]]
+flags_default_extra = []
+flags_thunderx_extra = [
+	['RTE_MACHINE', '"thunderx"'],
+	['RTE_USE_C11_MEM_MODEL', false]]
+
+machine_args_generic = [
+	['default', ['-march=armv8-a+crc+crypto']],
+	['native', ['-march=native']],
+	['0xd03', ['-mcpu=cortex-a53']],
+	['0xd04', ['-mcpu=cortex-a35']],
+	['0xd07', ['-mcpu=cortex-a57']],
+	['0xd08', ['-mcpu=cortex-a72']],
+	['0xd09', ['-mcpu=cortex-a73']],
+	['0xd0a', ['-mcpu=cortex-a75']]]
+
+machine_args_cavium = [
+	['default', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']],
+	['native', ['-march=native']],
+	['0xa1', ['-mcpu=thunderxt88'], flags_thunderx_extra],
+	['0xa2', ['-mcpu=thunderxt81'], flags_thunderx_extra],
+	['0xa3', ['-mcpu=thunderxt83'], flags_thunderx_extra]]
 
 ## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page G7-5321)
 impl_generic = ['Generic armv8', flags_generic, machine_args_generic]
@@ -157,8 +176,16 @@  else
 	endif
 	foreach marg: machine[2]
 		if marg[0] == impl_pn
-			foreach f: marg[1]
-				machine_args += f
+			foreach flag: marg[1]
+				if cc.has_argument(flag)
+					machine_args += flag
+				endif
+			endforeach
+			# Apply any extra machine specific flags.
+			foreach flag: marg.get(2, flags_default_extra)
+				if flag.length() > 0
+					dpdk_conf.set(flag[0], flag[1])
+				endif
 			endforeach
 		endif
 	endforeach