From patchwork Tue Feb 19 13:24:50 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrius Sirvys X-Patchwork-Id: 50366 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 4B2DD5942; Tue, 19 Feb 2019 14:25:37 +0100 (CET) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by dpdk.org (Postfix) with ESMTP id 5731358FA; Tue, 19 Feb 2019 14:25:35 +0100 (CET) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 19 Feb 2019 05:25:34 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.58,388,1544515200"; d="scan'208";a="125562984" Received: from silpixa00380299.ir.intel.com ([10.237.223.68]) by fmsmga008.fm.intel.com with ESMTP; 19 Feb 2019 05:25:30 -0800 From: Andrius Sirvys To: dev@dpdk.org, Ravi Kumar , Rasesh Mody , Shahed Shaikh , Ajit Khaparde , Somnath Kotur , Rahul Lakkireddy , Wenzhuo Lu , Alejandro Lucero , Keith Wiles Cc: Andrius Sirvys , stable@dpdk.org, stephen@networkplumber.org, shaguna@chelsio.com, rasesh.mody@qlogic.com, ophirmu@mellanox.com Date: Tue, 19 Feb 2019 13:24:50 +0000 Message-Id: <1550582690-29533-1-git-send-email-andrius.sirvys@intel.com> X-Mailer: git-send-email 2.7.4 Subject: [dpdk-dev] [PATCH] drivers/net: fix shifting 32-bit signed variable 31 times X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Shifting signed 32-bit values by 31-bits has the potential for unexpected outcomes as compiler can overwrite a bit. Specified that values are unsigned. Errors are observed from running cppcheck. Bugzilla ID: 58 Fixes: 69e209be5464 ("net/axgbe: add register map and related macros") Fixes: b5bf7719221d ("bnx2x: driver support routines") Fixes: ed2ced6fe927 ("net/bnxt: check initialization before accessing stats") Fixes: 6fda3f0ddda9 ("net/cxgbe: add API to program hardware MPS table") Fixes: bdb244b96920 ("e1000: whitespace changes") Fixes: 5a32a257f957 ("e1000: more NICs in base driver") Fixes: 2fe669f4bcd2 ("net/nfp: support MAC address change") Fixes: defb9a5dd156 ("nfp: introduce driver initialization") Fixes: ec94dbc57362 ("qede: add base driver") Fixes: d2e7d931d0ad ("net/qede/base: formatting changes") Fixes: cdc07e83bb24 ("net/tap: add eBPF program file") Cc: stable@dpdk.org Signed-off-by: Andrius Sirvys Reviewed-by: Ferruh Yigit --- Cc: ravi1.kumar@amd.com Cc: stephen@networkplumber.org Cc: ajit.khaparde@broadcom.com Cc: shaguna@chelsio.com Cc: alejandro.lucero@netronome.com Cc: rasesh.mody@qlogic.com Cc: ophirmu@mellanox.com --- drivers/net/axgbe/axgbe_common.h | 4 ++-- drivers/net/bnx2x/ecore_hsi.h | 2 +- drivers/net/bnx2x/ecore_reg.h | 2 +- drivers/net/bnx2x/elink.h | 2 +- drivers/net/bnxt/bnxt.h | 2 +- drivers/net/cxgbe/base/t4_hw.c | 2 +- drivers/net/e1000/base/e1000_82575.h | 4 ++-- drivers/net/e1000/base/e1000_ich8lan.c | 2 +- drivers/net/nfp/nfp_net_ctrl.h | 4 ++-- drivers/net/qede/base/common_hsi.h | 4 ++-- drivers/net/qede/base/ecore_hsi_common.h | 2 +- drivers/net/qede/base/ecore_hsi_eth.h | 2 +- drivers/net/qede/base/ecore_hw_defs.h | 2 +- drivers/net/tap/tap_bpf_program.c | 2 +- 14 files changed, 18 insertions(+), 18 deletions(-) diff --git a/drivers/net/axgbe/axgbe_common.h b/drivers/net/axgbe/axgbe_common.h index d25d54c..34f60f1 100644 --- a/drivers/net/axgbe/axgbe_common.h +++ b/drivers/net/axgbe/axgbe_common.h @@ -1351,9 +1351,9 @@ do { \ #define SET_BITS_LE(_var, _index, _width, _val) \ do { \ - (_var) &= rte_cpu_to_le_32(~(((0x1 << (_width)) - 1) << (_index)));\ + (_var) &= rte_cpu_to_le_32(~(((0x1U << (_width)) - 1) << (_index)));\ (_var) |= rte_cpu_to_le_32((((_val) & \ - ((0x1 << (_width)) - 1)) << (_index))); \ + ((0x1U << (_width)) - 1)) << (_index))); \ } while (0) /* Bit setting and getting macros based on register fields diff --git a/drivers/net/bnx2x/ecore_hsi.h b/drivers/net/bnx2x/ecore_hsi.h index 1192e5d..74189ee 100644 --- a/drivers/net/bnx2x/ecore_hsi.h +++ b/drivers/net/bnx2x/ecore_hsi.h @@ -3545,7 +3545,7 @@ struct igu_regular #define IGU_REGULAR_CLEANUP_TYPE_SHIFT 28 #define IGU_REGULAR_CLEANUP_SET (0x1<<30) /* BitField sb_id_and_flags */ #define IGU_REGULAR_CLEANUP_SET_SHIFT 30 -#define IGU_REGULAR_BCLEANUP (0x1<<31) /* BitField sb_id_and_flags */ +#define IGU_REGULAR_BCLEANUP (0x1U<<31) /* BitField sb_id_and_flags */ #define IGU_REGULAR_BCLEANUP_SHIFT 31 uint32_t reserved_2; }; diff --git a/drivers/net/bnx2x/ecore_reg.h b/drivers/net/bnx2x/ecore_reg.h index d69e857..7af9a2d 100644 --- a/drivers/net/bnx2x/ecore_reg.h +++ b/drivers/net/bnx2x/ecore_reg.h @@ -1981,7 +1981,7 @@ #define AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR (0x1<<5) #define AEU_INPUTS_ATTN_BITS_BRB_HW_INTERRUPT (0x1<<19) #define AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR (0x1<<18) -#define AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT (0x1<<31) +#define AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT (0x1U<<31) #define AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR (0x1<<30) #define AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT (0x1<<9) #define AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR (0x1<<8) diff --git a/drivers/net/bnx2x/elink.h b/drivers/net/bnx2x/elink.h index c8b08bc..dd70ac6 100644 --- a/drivers/net/bnx2x/elink.h +++ b/drivers/net/bnx2x/elink.h @@ -440,7 +440,7 @@ struct elink_params { #define ELINK_EEE_MODE_OUTPUT_TIME (1 << 28) #define ELINK_EEE_MODE_OVERRIDE_NVRAM (1 << 29) #define ELINK_EEE_MODE_ENABLE_LPI (1 << 30) -#define ELINK_EEE_MODE_ADV_LPI (1 << 31) +#define ELINK_EEE_MODE_ADV_LPI (1U << 31) uint16_t hw_led_mode; /* part of the hw_config read from the shmem */ uint32_t multi_phy_config; diff --git a/drivers/net/bnxt/bnxt.h b/drivers/net/bnxt/bnxt.h index f75b0ad..5535c37 100644 --- a/drivers/net/bnxt/bnxt.h +++ b/drivers/net/bnxt/bnxt.h @@ -263,7 +263,7 @@ struct bnxt { #define BNXT_FLAG_TRUSTED_VF_EN (1 << 11) #define BNXT_FLAG_DFLT_VNIC_SET (1 << 12) #define BNXT_FLAG_NEW_RM (1 << 30) -#define BNXT_FLAG_INIT_DONE (1 << 31) +#define BNXT_FLAG_INIT_DONE (1U << 31) #define BNXT_PF(bp) (!((bp)->flags & BNXT_FLAG_VF)) #define BNXT_VF(bp) ((bp)->flags & BNXT_FLAG_VF) #define BNXT_NPAR(bp) ((bp)->port_partition_type) diff --git a/drivers/net/cxgbe/base/t4_hw.c b/drivers/net/cxgbe/base/t4_hw.c index 796e2f7..71ad1cb 100644 --- a/drivers/net/cxgbe/base/t4_hw.c +++ b/drivers/net/cxgbe/base/t4_hw.c @@ -4246,7 +4246,7 @@ int t4_free_raw_mac_filt(struct adapter *adap, unsigned int viid, V_FW_CMD_EXEC(0) | V_FW_VI_MAC_CMD_VIID(viid)); raw = V_FW_VI_MAC_CMD_ENTRY_TYPE(FW_VI_MAC_TYPE_RAW); - c.freemacs_to_len16 = cpu_to_be32(V_FW_VI_MAC_CMD_FREEMACS(0) | + c.freemacs_to_len16 = cpu_to_be32(V_FW_VI_MAC_CMD_FREEMACS(0U) | raw | V_FW_CMD_LEN16(1)); diff --git a/drivers/net/e1000/base/e1000_82575.h b/drivers/net/e1000/base/e1000_82575.h index 4133cdd..6f2b22c 100644 --- a/drivers/net/e1000/base/e1000_82575.h +++ b/drivers/net/e1000/base/e1000_82575.h @@ -383,7 +383,7 @@ struct e1000_adv_tx_context_desc { #define E1000_ETQF_FILTER_ENABLE (1 << 26) #define E1000_ETQF_IMM_INT (1 << 29) #define E1000_ETQF_1588 (1 << 30) -#define E1000_ETQF_QUEUE_ENABLE (1 << 31) +#define E1000_ETQF_QUEUE_ENABLE (1U << 31) /* * ETQF filter list: one static filter per filter consumer. This is * to avoid filter collisions later. Add new filters @@ -410,7 +410,7 @@ struct e1000_adv_tx_context_desc { #define E1000_DTXSWC_LLE_MASK 0x00FF0000 /* Per VF Local LB enables */ #define E1000_DTXSWC_VLAN_SPOOF_SHIFT 8 #define E1000_DTXSWC_LLE_SHIFT 16 -#define E1000_DTXSWC_VMDQ_LOOPBACK_EN (1 << 31) /* global VF LB enable */ +#define E1000_DTXSWC_VMDQ_LOOPBACK_EN (1U << 31) /* global VF LB enable */ /* Easy defines for setting default pool, would normally be left a zero */ #define E1000_VT_CTL_DEFAULT_POOL_SHIFT 7 diff --git a/drivers/net/e1000/base/e1000_ich8lan.c b/drivers/net/e1000/base/e1000_ich8lan.c index 92ab6fc..2654a18 100644 --- a/drivers/net/e1000/base/e1000_ich8lan.c +++ b/drivers/net/e1000/base/e1000_ich8lan.c @@ -5166,7 +5166,7 @@ STATIC void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw) /* Device Status */ if (hw->mac.type == e1000_ich8lan) { reg = E1000_READ_REG(hw, E1000_STATUS); - reg &= ~(1 << 31); + reg &= ~(1U << 31); E1000_WRITE_REG(hw, E1000_STATUS, reg); } diff --git a/drivers/net/nfp/nfp_net_ctrl.h b/drivers/net/nfp/nfp_net_ctrl.h index 21e17da..fc3540a 100644 --- a/drivers/net/nfp/nfp_net_ctrl.h +++ b/drivers/net/nfp/nfp_net_ctrl.h @@ -122,7 +122,7 @@ #define NFP_NET_CFG_CTRL_MSIX_TX_OFF (0x1 << 26) /* Disable MSIX for TX */ #define NFP_NET_CFG_CTRL_LSO2 (0x1 << 28) /* LSO/TSO (version 2) */ #define NFP_NET_CFG_CTRL_RSS2 (0x1 << 29) /* RSS (version 2) */ -#define NFP_NET_CFG_CTRL_LIVE_ADDR (0x1 << 31) /* live MAC addr change */ +#define NFP_NET_CFG_CTRL_LIVE_ADDR (0x1U << 31)/* live MAC addr change */ #define NFP_NET_CFG_UPDATE 0x0004 #define NFP_NET_CFG_UPDATE_GEN (0x1 << 0) /* General update */ #define NFP_NET_CFG_UPDATE_RING (0x1 << 1) /* Ring config change */ @@ -135,7 +135,7 @@ #define NFP_NET_CFG_UPDATE_IRQMOD (0x1 << 8) /* IRQ mod change */ #define NFP_NET_CFG_UPDATE_VXLAN (0x1 << 9) /* VXLAN port change */ #define NFP_NET_CFG_UPDATE_MACADDR (0x1 << 11) /* MAC address change */ -#define NFP_NET_CFG_UPDATE_ERR (0x1 << 31) /* A error occurred */ +#define NFP_NET_CFG_UPDATE_ERR (0x1U << 31) /* A error occurred */ #define NFP_NET_CFG_TXRS_ENABLE 0x0008 #define NFP_NET_CFG_RXRS_ENABLE 0x0010 #define NFP_NET_CFG_MTU 0x0018 diff --git a/drivers/net/qede/base/common_hsi.h b/drivers/net/qede/base/common_hsi.h index 2aaf298..7047eb9 100644 --- a/drivers/net/qede/base/common_hsi.h +++ b/drivers/net/qede/base/common_hsi.h @@ -400,9 +400,9 @@ #define QM_BYTE_CRD_REG_WIDTH 24 #define QM_BYTE_CRD_REG_SIGN_BIT (1 << (QM_BYTE_CRD_REG_WIDTH - 1)) #define QM_WFQ_CRD_REG_WIDTH 32 -#define QM_WFQ_CRD_REG_SIGN_BIT (1 << (QM_WFQ_CRD_REG_WIDTH - 1)) +#define QM_WFQ_CRD_REG_SIGN_BIT (1U << (QM_WFQ_CRD_REG_WIDTH - 1)) #define QM_RL_CRD_REG_WIDTH 32 -#define QM_RL_CRD_REG_SIGN_BIT (1 << (QM_RL_CRD_REG_WIDTH - 1)) +#define QM_RL_CRD_REG_SIGN_BIT (1U << (QM_RL_CRD_REG_WIDTH - 1)) /*****************/ /* CAU CONSTANTS */ diff --git a/drivers/net/qede/base/ecore_hsi_common.h b/drivers/net/qede/base/ecore_hsi_common.h index 6d4a4dd..2ce0ea9 100644 --- a/drivers/net/qede/base/ecore_hsi_common.h +++ b/drivers/net/qede/base/ecore_hsi_common.h @@ -2250,7 +2250,7 @@ struct igu_cleanup { #define IGU_CLEANUP_CLEANUP_TYPE_MASK 0x7 #define IGU_CLEANUP_CLEANUP_TYPE_SHIFT 28 /* must always be set (use enum command_type_bit) */ -#define IGU_CLEANUP_COMMAND_TYPE_MASK 0x1 +#define IGU_CLEANUP_COMMAND_TYPE_MASK 0x1U #define IGU_CLEANUP_COMMAND_TYPE_SHIFT 31 __le32 reserved1; }; diff --git a/drivers/net/qede/base/ecore_hsi_eth.h b/drivers/net/qede/base/ecore_hsi_eth.h index 158ca67..7bc0947 100644 --- a/drivers/net/qede/base/ecore_hsi_eth.h +++ b/drivers/net/qede/base/ecore_hsi_eth.h @@ -2420,7 +2420,7 @@ struct gft_ram_line { #define GFT_RAM_LINE_TCP_FLAG_NS_SHIFT 29 #define GFT_RAM_LINE_DST_PORT_MASK 0x1 #define GFT_RAM_LINE_DST_PORT_SHIFT 30 -#define GFT_RAM_LINE_SRC_PORT_MASK 0x1 +#define GFT_RAM_LINE_SRC_PORT_MASK 0x1U #define GFT_RAM_LINE_SRC_PORT_SHIFT 31 __le32 hi; #define GFT_RAM_LINE_DSCP_MASK 0x1 diff --git a/drivers/net/qede/base/ecore_hw_defs.h b/drivers/net/qede/base/ecore_hw_defs.h index b8c2686..92361e7 100644 --- a/drivers/net/qede/base/ecore_hw_defs.h +++ b/drivers/net/qede/base/ecore_hw_defs.h @@ -51,7 +51,7 @@ struct igu_ctrl_reg { #define IGU_CTRL_REG_PXP_ADDR_SHIFT 16 #define IGU_CTRL_REG_RESERVED_MASK 0x1 #define IGU_CTRL_REG_RESERVED_SHIFT 28 -#define IGU_CTRL_REG_TYPE_MASK 0x1 /* use enum igu_ctrl_cmd */ +#define IGU_CTRL_REG_TYPE_MASK 0x1U /* use enum igu_ctrl_cmd */ #define IGU_CTRL_REG_TYPE_SHIFT 31 }; diff --git a/drivers/net/tap/tap_bpf_program.c b/drivers/net/tap/tap_bpf_program.c index 1cb7382..532e883 100644 --- a/drivers/net/tap/tap_bpf_program.c +++ b/drivers/net/tap/tap_bpf_program.c @@ -106,7 +106,7 @@ rte_softrss_be(const __u32 *input_tuple, const uint8_t *rss_key, for (j = 0; j < input_len; j++) { #pragma unroll for (i = 0; i < 32; i++) { - if (input_tuple[j] & (1 << (31 - i))) { + if (input_tuple[j] & (1U << (31 - i))) { hash ^= ((const __u32 *)def_rss_key)[j] << i | (__u32)((uint64_t) (((const __u32 *)def_rss_key)[j + 1])