From patchwork Wed Feb 13 08:54:13 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Zhao1, Wei" X-Patchwork-Id: 50296 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id AC8FE7CDA; Wed, 13 Feb 2019 10:20:55 +0100 (CET) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by dpdk.org (Postfix) with ESMTP id 514A05F62 for ; Wed, 13 Feb 2019 10:20:54 +0100 (CET) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga106.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 13 Feb 2019 01:20:53 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.58,365,1544515200"; d="scan'208";a="126088946" Received: from dpdk6.bj.intel.com ([172.16.182.192]) by orsmga003.jf.intel.com with ESMTP; 13 Feb 2019 01:20:51 -0800 From: Wei Zhao To: dev@dpdk.org Cc: jingjing.wu@intel.com, qi.z.zhang@intel.com, Wei Zhao Date: Wed, 13 Feb 2019 16:54:13 +0800 Message-Id: <1550048053-27288-1-git-send-email-wei.zhao1@intel.com> X-Mailer: git-send-email 2.7.5 Subject: [dpdk-dev] [PATCH] net/avf: enable admin queue interrupt X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" There is need to enble CLEARPBA bit for ice NIC of A0/A1 version in order to enable admin queue interrupt in avf mode. If not, avf will not work. Signed-off-by: Wei Zhao Acked-by: Qi Zhang --- drivers/net/avf/avf_ethdev.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/avf/avf_ethdev.c b/drivers/net/avf/avf_ethdev.c index 13eec1b..797f505 100644 --- a/drivers/net/avf/avf_ethdev.c +++ b/drivers/net/avf/avf_ethdev.c @@ -1159,7 +1159,7 @@ avf_enable_irq0(struct avf_hw *hw) AVF_WRITE_REG(hw, AVFINT_ICR0_ENA1, AVFINT_ICR0_ENA1_ADMINQ_MASK); AVF_WRITE_REG(hw, AVFINT_DYN_CTL01, AVFINT_DYN_CTL01_INTENA_MASK | - AVFINT_DYN_CTL01_ITR_INDX_MASK); + AVFINT_DYN_CTL01_CLEARPBA_MASK | AVFINT_DYN_CTL01_ITR_INDX_MASK); AVF_WRITE_FLUSH(hw); }