From patchwork Mon Jan 7 06:16:14 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Zhao1, Wei" X-Patchwork-Id: 49455 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 2B48F1B463; Mon, 7 Jan 2019 07:41:49 +0100 (CET) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by dpdk.org (Postfix) with ESMTP id 18A085F34; Mon, 7 Jan 2019 07:41:46 +0100 (CET) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga107.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 06 Jan 2019 22:41:45 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.56,450,1539673200"; d="scan'208";a="123826821" Received: from dpdk6.bj.intel.com ([172.16.182.192]) by FMSMGA003.fm.intel.com with ESMTP; 06 Jan 2019 22:41:44 -0800 From: Wei Zhao To: dev@dpdk.org Cc: stable@dpdk.org, qi.z.zhang@intel.com, jingjing.wu@intel.com, Wei Zhao Date: Mon, 7 Jan 2019 14:16:14 +0800 Message-Id: <1546841774-15676-1-git-send-email-wei.zhao1@intel.com> X-Mailer: git-send-email 2.7.5 In-Reply-To: <11546839569-13787-1-git-send-email-wei.zhao1@intel.com> References: <11546839569-13787-1-git-send-email-wei.zhao1@intel.com> Subject: [dpdk-dev] [PATCH v4] net/ixgbe: fix multicast table enable error for VF X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" In ixgbe PMD code, all vf ars set with bit IXGBE_VMOLR_ROMPE, which make vf accept packets that match the MTA table, if some vf update IXGBE_MTA in function ixgbe_vf_set_multicast, then all vf will receive packets from these address. So there is need to set VMOLR register bit ROPE only after this vf has been set multicast address. If this bit is set when pf host doing initialization, this vf will receive multicast packets with address written in MTA table.And also disable MTA when detect entry number of MAC address is 0 of configuration from vf. Align to ixgbe pf kernel 5.3.7 code to fix this bug. Fixes: 00e30184daa0 ("ixgbe: add PF support") Signed-off-by: Wei Zhao --- v2: change patch name and fix typo in log. v3: fix typo and disable MTA when detect all zero MAC address configuration. v4: change code to disable MTA when detect entry number of MAC address is 0 of configuration from vf. --- drivers/net/ixgbe/ixgbe_pf.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/net/ixgbe/ixgbe_pf.c b/drivers/net/ixgbe/ixgbe_pf.c index 4b833ff..4e4d39a 100644 --- a/drivers/net/ixgbe/ixgbe_pf.c +++ b/drivers/net/ixgbe/ixgbe_pf.c @@ -351,7 +351,7 @@ ixgbe_vf_reset_event(struct rte_eth_dev *dev, uint16_t vf) int rar_entry = hw->mac.num_rar_entries - (vf + 1); uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(vf)); - vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_ROMPE | + vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE); IXGBE_WRITE_REG(hw, IXGBE_VMOLR(vf), vmolr); @@ -503,6 +503,7 @@ ixgbe_vf_set_multicast(struct rte_eth_dev *dev, uint32_t vf, uint32_t *msgbuf) const uint32_t IXGBE_MTA_BIT_MASK = (0x1 << IXGBE_MTA_BIT_SHIFT) - 1; uint32_t reg_val; int i; + u32 vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(vf)); /* Disable multicast promiscuous first */ ixgbe_disable_vf_mc_promisc(dev, vf); @@ -516,6 +517,12 @@ ixgbe_vf_set_multicast(struct rte_eth_dev *dev, uint32_t vf, uint32_t *msgbuf) vfinfo->vf_mc_hashes[i] = hash_list[i]; } + if (!nb_entries) { + vmolr &= ~IXGBE_VMOLR_ROMPE; + IXGBE_WRITE_REG(hw, IXGBE_VMOLR(vf), vmolr); + return 0; + } + for (i = 0; i < vfinfo->num_vf_mc_hashes; i++) { mta_idx = (vfinfo->vf_mc_hashes[i] >> IXGBE_MTA_BIT_SHIFT) & IXGBE_MTA_INDEX_MASK; @@ -525,6 +532,9 @@ ixgbe_vf_set_multicast(struct rte_eth_dev *dev, uint32_t vf, uint32_t *msgbuf) IXGBE_WRITE_REG(hw, IXGBE_MTA(mta_idx), reg_val); } + vmolr |= IXGBE_VMOLR_ROMPE; + IXGBE_WRITE_REG(hw, IXGBE_VMOLR(vf), vmolr); + return 0; }