diff mbox series

[11/20] net/i40e/base: correct global reset timeout calculation

Message ID 20180925023442.134705-12-qi.z.zhang@intel.com (mailing list archive)
State Accepted, archived
Delegated to: Qi Zhang
Headers
Series base code update |

Checks

Context Check Description
ci/checkpatch success coding style OK
ci/Intel-compilation success Compilation OK

Commit Message

Qi Zhang Sept. 25, 2018, 2:34 a.m. UTC 
  The wait time for Global Reset Ready steady state is calculated based on
the GLGEN_RSTCTL.GRSTDEL value. However, current impelementation multiplied
that value by 20 as a workaround for an issue in SOC platforms.
This resulted in the maximum GLGEN_RSTCTL.GRSTDEL timeout of 6.5 seconds
becoming 130 seconds, which is so long that the VMkernel watchdog thinks
the kernel is frozen and triggers a PSOD.

Cc: stable@dpdk.org

Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
 drivers/net/i40e/base/i40e_common.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
diff mbox series

Patch

diff --git a/drivers/net/i40e/base/i40e_common.c b/drivers/net/i40e/base/i40e_common.c
index 0affa98ac..0eb369ff6 100644
--- a/drivers/net/i40e/base/i40e_common.c
+++ b/drivers/net/i40e/base/i40e_common.c
@@ -1342,7 +1342,7 @@  enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw)
 			I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>
 			I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
 
-	grst_del = grst_del * 20;
+	grst_del = min(grst_del * 20, 160U);
 
 	for (cnt = 0; cnt < grst_del; cnt++) {
 		reg = rd32(hw, I40E_GLGEN_RSTAT);