From patchwork Mon Sep 24 13:50:27 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Rybchenko X-Patchwork-Id: 45211 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 768B158F6; Mon, 24 Sep 2018 15:51:12 +0200 (CEST) Received: from dispatch1-us1.ppe-hosted.com (dispatch1-us1.ppe-hosted.com [148.163.129.52]) by dpdk.org (Postfix) with ESMTP id 12D262BF4 for ; Mon, 24 Sep 2018 15:50:52 +0200 (CEST) X-Virus-Scanned: Proofpoint Essentials engine Received: from webmail.solarflare.com (webmail.solarflare.com [12.187.104.26]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-SHA384 (256/256 bits)) (No client certificate requested) by mx1-us3.ppe-hosted.com (Proofpoint Essentials ESMTP Server) with ESMTPS id CA897B40087 for ; Mon, 24 Sep 2018 13:50:50 +0000 (UTC) Received: from ocex03.SolarFlarecom.com (10.20.40.36) by ocex03.SolarFlarecom.com (10.20.40.36) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Mon, 24 Sep 2018 06:50:47 -0700 Received: from opal.uk.solarflarecom.com (10.17.10.1) by ocex03.SolarFlarecom.com (10.20.40.36) with Microsoft SMTP Server (TLS) id 15.0.1395.4 via Frontend Transport; Mon, 24 Sep 2018 06:50:47 -0700 Received: from ukv-loginhost.uk.solarflarecom.com (ukv-loginhost.uk.solarflarecom.com [10.17.10.39]) by opal.uk.solarflarecom.com (8.13.8/8.13.8) with ESMTP id w8ODojsh014556; Mon, 24 Sep 2018 14:50:45 +0100 Received: from ukv-loginhost.uk.solarflarecom.com (localhost [127.0.0.1]) by ukv-loginhost.uk.solarflarecom.com (Postfix) with ESMTP id D7E921626D1; Mon, 24 Sep 2018 14:50:45 +0100 (BST) From: Andrew Rybchenko To: CC: Tom Millington Date: Mon, 24 Sep 2018 14:50:27 +0100 Message-ID: <1537797030-26548-9-git-send-email-arybchenko@solarflare.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1537797030-26548-1-git-send-email-arybchenko@solarflare.com> References: <1537797030-26548-1-git-send-email-arybchenko@solarflare.com> MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-12.5.0.1300-8.5.1010-24114.005 X-TM-AS-Result: No-0.699600-4.000000-10 X-TMASE-MatchedRID: 8hqU3tU3q+B8tzbYIxQT62ivjLE8DPtZ1JGHfxYWjYfMSJVVqDHzVhlm 50zOyWbd0fzQGQC+A5215EbLBWcBdyY0eULsNBXlA9lly13c/gH6e9LB8NtoJdQzSBS2jTC48FS rkmy6/FIWnw4IW0ouLrK0FbOnC9Zrab7iwIkpl7AtMfCdg6KRDXG54hbZ8q7I2dPiOwoLDVVqBb WChvoV/FgQa+1D8MG6JbqK7bFjWTtg5AA4n45LbZ4CIKY/Hg3AGdQnQSTrKGPEQdG7H66TyHEqm 8QYBtMOpzxnU4e0Wn2y9skB5eZI6RQmptPsEVNZlPiw1QvHnqhdu7XD0KGkCRk9KzKpFsnTFH2T gzlvD0tVAidBv2T7mDU89hPgULqYk3UkV5Qp4wSI45Rd9ORJwFlJvEhEss3fzQahrdQz77w= X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--0.699600-4.000000 X-TMASE-Version: SMEX-12.5.0.1300-8.5.1010-24114.005 X-MDID: 1537797051-1EIoG1AvJ-EB Subject: [dpdk-dev] [PATCH 08/11] net/sfc/base: guard Rx scale code with corresponding option X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Tom Millington Previously only some of the code was guarded by this which caused a build error when EFSYS_OPT_RX_SCALE is 0 (e.g. in manftest). Signed-off-by: Tom Millington Signed-off-by: Andrew Rybchenko --- drivers/net/sfc/base/ef10_nic.c | 7 +++++++ drivers/net/sfc/base/efx.h | 2 ++ drivers/net/sfc/base/siena_nic.c | 2 ++ 3 files changed, 11 insertions(+) diff --git a/drivers/net/sfc/base/ef10_nic.c b/drivers/net/sfc/base/ef10_nic.c index c197ff957..1b3d60682 100644 --- a/drivers/net/sfc/base/ef10_nic.c +++ b/drivers/net/sfc/base/ef10_nic.c @@ -1086,11 +1086,13 @@ ef10_get_datapath_caps( } encp->enc_rx_prefix_size = 14; +#if EFSYS_OPT_RX_SCALE /* Check if the firmware supports additional RSS modes */ if (CAP_FLAGS1(req, ADDITIONAL_RSS_MODES)) encp->enc_rx_scale_additional_modes_supported = B_TRUE; else encp->enc_rx_scale_additional_modes_supported = B_FALSE; +#endif /* EFSYS_OPT_RX_SCALE */ /* Check if the firmware supports TSO */ if (CAP_FLAGS1(req, TX_TSO)) @@ -1296,6 +1298,7 @@ ef10_get_datapath_caps( else encp->enc_hlb_counters = B_FALSE; +#if EFSYS_OPT_RX_SCALE if (CAP_FLAGS1(req, RX_RSS_LIMITED)) { /* Only one exclusive RSS context is available per port. */ encp->enc_rx_scale_max_exclusive_contexts = 1; @@ -1345,6 +1348,8 @@ ef10_get_datapath_caps( */ encp->enc_rx_scale_l4_hash_supported = B_TRUE; } +#endif /* EFSYS_OPT_RX_SCALE */ + /* Check if the firmware supports "FLAG" and "MARK" filter actions */ if (CAP_FLAGS2(req, FILTER_ACTION_FLAG)) encp->enc_filter_action_flag_supported = B_TRUE; @@ -1368,8 +1373,10 @@ ef10_get_datapath_caps( return (0); +#if EFSYS_OPT_RX_SCALE fail5: EFSYS_PROBE(fail5); +#endif /* EFSYS_OPT_RX_SCALE */ fail4: EFSYS_PROBE(fail4); fail3: diff --git a/drivers/net/sfc/base/efx.h b/drivers/net/sfc/base/efx.h index a8c3ae301..246708f9c 100644 --- a/drivers/net/sfc/base/efx.h +++ b/drivers/net/sfc/base/efx.h @@ -1281,6 +1281,7 @@ typedef struct efx_nic_cfg_s { uint32_t enc_rx_prefix_size; uint32_t enc_rx_buf_align_start; uint32_t enc_rx_buf_align_end; +#if EFSYS_OPT_RX_SCALE uint32_t enc_rx_scale_max_exclusive_contexts; /* * Mask of supported hash algorithms. @@ -1293,6 +1294,7 @@ typedef struct efx_nic_cfg_s { */ boolean_t enc_rx_scale_l4_hash_supported; boolean_t enc_rx_scale_additional_modes_supported; +#endif /* EFSYS_OPT_RX_SCALE */ #if EFSYS_OPT_LOOPBACK efx_qword_t enc_loopback_types[EFX_LINK_NMODES]; #endif /* EFSYS_OPT_LOOPBACK */ diff --git a/drivers/net/sfc/base/siena_nic.c b/drivers/net/sfc/base/siena_nic.c index 8a58986e8..fca17171b 100644 --- a/drivers/net/sfc/base/siena_nic.c +++ b/drivers/net/sfc/base/siena_nic.c @@ -114,6 +114,7 @@ siena_board_cfg( /* Alignment for WPTR updates */ encp->enc_rx_push_align = 1; +#if EFSYS_OPT_RX_SCALE /* There is one RSS context per function */ encp->enc_rx_scale_max_exclusive_contexts = 1; @@ -128,6 +129,7 @@ siena_board_cfg( /* There is no support for additional RSS modes */ encp->enc_rx_scale_additional_modes_supported = B_FALSE; +#endif /* EFSYS_OPT_RX_SCALE */ encp->enc_tx_dma_desc_size_max = EFX_MASK32(FSF_AZ_TX_KER_BYTE_COUNT); /* Fragments must not span 4k boundaries. */