From patchwork Mon Sep 10 09:33:34 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Rybchenko X-Patchwork-Id: 44500 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id E7EEC1B001; Mon, 10 Sep 2018 11:34:44 +0200 (CEST) Received: from dispatch1-us1.ppe-hosted.com (dispatch1-us1.ppe-hosted.com [67.231.154.164]) by dpdk.org (Postfix) with ESMTP id 253E24CA7 for ; Mon, 10 Sep 2018 11:33:55 +0200 (CEST) X-Virus-Scanned: Proofpoint Essentials engine Received: from webmail.solarflare.com (webmail.solarflare.com [12.187.104.26]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-SHA384 (256/256 bits)) (No client certificate requested) by mx1-us1.ppe-hosted.com (Proofpoint Essentials ESMTP Server) with ESMTPS id 0F7D5780055 for ; Mon, 10 Sep 2018 09:33:54 +0000 (UTC) Received: from ocex03.SolarFlarecom.com (10.20.40.36) by ocex03.SolarFlarecom.com (10.20.40.36) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Mon, 10 Sep 2018 02:33:49 -0700 Received: from opal.uk.solarflarecom.com (10.17.10.1) by ocex03.SolarFlarecom.com (10.20.40.36) with Microsoft SMTP Server (TLS) id 15.0.1395.4 via Frontend Transport; Mon, 10 Sep 2018 02:33:48 -0700 Received: from ukv-loginhost.uk.solarflarecom.com (ukv-loginhost.uk.solarflarecom.com [10.17.10.39]) by opal.uk.solarflarecom.com (8.13.8/8.13.8) with ESMTP id w8A9Xlas023891; Mon, 10 Sep 2018 10:33:47 +0100 Received: from ukv-loginhost.uk.solarflarecom.com (localhost [127.0.0.1]) by ukv-loginhost.uk.solarflarecom.com (Postfix) with ESMTP id 45F8A1626D2; Mon, 10 Sep 2018 10:33:47 +0100 (BST) From: Andrew Rybchenko To: CC: Richard Houldsworth Date: Mon, 10 Sep 2018 10:33:34 +0100 Message-ID: <1536572016-18134-36-git-send-email-arybchenko@solarflare.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1536572016-18134-1-git-send-email-arybchenko@solarflare.com> References: <1536572016-18134-1-git-send-email-arybchenko@solarflare.com> MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-12.5.0.1300-8.5.1010-24084.005 X-TM-AS-Result: No-5.059700-4.000000-10 X-TMASE-MatchedRID: I0XPGJpOaREmcsJib2Ijae7KTDtx8CggZORgGu5KV7cs/uUAk6xP7F/2 zKXxjR59nmkKx4n0E8gQEZaWew/4U200sCPwNg7wQ1OcCEvT+bdwG8b5skjkoPHFoBcOsKezpux EEXVQG1yw3CreLeI86IAy6p60ZV62fJ5/bZ6npdg7AFczfjr/7DiXiVQPFXqXeH0DzzuhHbY95n dQwWf+5iUX958IC9wHEJceb6pkk4Q= X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--5.059700-4.000000 X-TMASE-Version: SMEX-12.5.0.1300-8.5.1010-24084.005 X-MDID: 1536572034-S_n7_WdDVGuS Subject: [dpdk-dev] [PATCH 35/37] net/sfc/base: modify phy caps to indicate FEC request X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Richard Houldsworth The capability bits to request FEC modes are implicitly valid when the corresponding FEC mode is a supported capability. Drivers expect that it is only valid to advertise those capabilities explicitly marked as supported. The capabilities reported by firmware is modified with the implicit capabilities to present the explicit model to drivers. Signed-off-by: Richard Houldsworth Signed-off-by: Andrew Rybchenko --- drivers/net/sfc/base/ef10_nic.c | 15 +++++++++++++++ drivers/net/sfc/base/efx_phy.c | 8 +------- 2 files changed, 16 insertions(+), 7 deletions(-) diff --git a/drivers/net/sfc/base/ef10_nic.c b/drivers/net/sfc/base/ef10_nic.c index 0a2474f3e..b54cd3940 100644 --- a/drivers/net/sfc/base/ef10_nic.c +++ b/drivers/net/sfc/base/ef10_nic.c @@ -1772,6 +1772,21 @@ ef10_nic_board_cfg( if ((rc = efx_mcdi_get_phy_cfg(enp)) != 0) goto fail6; + /* + * Firmware with support for *_FEC capability bits does not + * report that the corresponding *_FEC_REQUESTED bits are supported. + * Add them here so that drivers understand that they are supported. + */ + if (epp->ep_phy_cap_mask & (1u << EFX_PHY_CAP_BASER_FEC)) + epp->ep_phy_cap_mask |= + (1u << EFX_PHY_CAP_BASER_FEC_REQUESTED); + if (epp->ep_phy_cap_mask & (1u << EFX_PHY_CAP_RS_FEC)) + epp->ep_phy_cap_mask |= + (1u << EFX_PHY_CAP_RS_FEC_REQUESTED); + if (epp->ep_phy_cap_mask & (1u << EFX_PHY_CAP_25G_BASER_FEC)) + epp->ep_phy_cap_mask |= + (1u << EFX_PHY_CAP_25G_BASER_FEC_REQUESTED); + /* Obtain the default PHY advertised capabilities */ if ((rc = ef10_phy_get_link(enp, &els)) != 0) goto fail7; diff --git a/drivers/net/sfc/base/efx_phy.c b/drivers/net/sfc/base/efx_phy.c index 7c341e429..25059dfe1 100644 --- a/drivers/net/sfc/base/efx_phy.c +++ b/drivers/net/sfc/base/efx_phy.c @@ -192,11 +192,6 @@ efx_phy_adv_cap_get( } } -#define EFX_PHY_CAP_FEC_REQ_MASK \ - (1U << EFX_PHY_CAP_BASER_FEC_REQUESTED) | \ - (1U << EFX_PHY_CAP_RS_FEC_REQUESTED) | \ - (1U << EFX_PHY_CAP_25G_BASER_FEC_REQUESTED) - __checkReturn efx_rc_t efx_phy_adv_cap_set( __in efx_nic_t *enp, @@ -210,8 +205,7 @@ efx_phy_adv_cap_set( EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT); - /* Ignore don't care bits of FEC (FEC EFX_PHY_CAP_*_REQUESTED) */ - if ((mask & ~(epp->ep_phy_cap_mask | EFX_PHY_CAP_FEC_REQ_MASK)) != 0) { + if ((mask & ~epp->ep_phy_cap_mask) != 0) { rc = ENOTSUP; goto fail1; }