From patchwork Mon Sep 10 09:33:21 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Rybchenko X-Patchwork-Id: 44492 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 7CFB77ED7; Mon, 10 Sep 2018 11:34:35 +0200 (CEST) Received: from dispatch1-us1.ppe-hosted.com (dispatch1-us1.ppe-hosted.com [67.231.154.164]) by dpdk.org (Postfix) with ESMTP id BE9B24C94 for ; Mon, 10 Sep 2018 11:33:53 +0200 (CEST) X-Virus-Scanned: Proofpoint Essentials engine Received: from webmail.solarflare.com (webmail.solarflare.com [12.187.104.26]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-SHA384 (256/256 bits)) (No client certificate requested) by mx1-us1.ppe-hosted.com (Proofpoint Essentials ESMTP Server) with ESMTPS id CBFCA780055 for ; Mon, 10 Sep 2018 09:33:52 +0000 (UTC) Received: from ocex03.SolarFlarecom.com (10.20.40.36) by ocex03.SolarFlarecom.com (10.20.40.36) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Mon, 10 Sep 2018 02:33:48 -0700 Received: from opal.uk.solarflarecom.com (10.17.10.1) by ocex03.SolarFlarecom.com (10.20.40.36) with Microsoft SMTP Server (TLS) id 15.0.1395.4 via Frontend Transport; Mon, 10 Sep 2018 02:33:47 -0700 Received: from ukv-loginhost.uk.solarflarecom.com (ukv-loginhost.uk.solarflarecom.com [10.17.10.39]) by opal.uk.solarflarecom.com (8.13.8/8.13.8) with ESMTP id w8A9XkuI023833; Mon, 10 Sep 2018 10:33:46 +0100 Received: from ukv-loginhost.uk.solarflarecom.com (localhost [127.0.0.1]) by ukv-loginhost.uk.solarflarecom.com (Postfix) with ESMTP id 53D771626D1; Mon, 10 Sep 2018 10:33:46 +0100 (BST) From: Andrew Rybchenko To: CC: Mark Spender Date: Mon, 10 Sep 2018 10:33:21 +0100 Message-ID: <1536572016-18134-23-git-send-email-arybchenko@solarflare.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1536572016-18134-1-git-send-email-arybchenko@solarflare.com> References: <1536572016-18134-1-git-send-email-arybchenko@solarflare.com> MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-12.5.0.1300-8.5.1010-24084.005 X-TM-AS-Result: No-2.838600-4.000000-10 X-TMASE-MatchedRID: vx0VEa8NezHANTc0UpB7DpFVDMlVCkWexLtUkmJKh3RFNyTs3OcE/+yG Sbx/RoQs3bzvU6za9nBFcQlq8WbRMH1GcR5AeEs7QpxiLlDD9FVA8I/PJy4EUx2OuJ8WKX6VcHj giTON9jJO9UxJ8vboSW8iEzpyogaofyoI97TEvxDYhNMNlv+0N5xfK35V7okVv8D7QPW2jo8kyE BGmhV5v+LzNWBegCW2wgn7iDBesS0nRE+fI6etknqxbHMX+iHCFdMIhyIJje+XXI0Xm2ReiXma0 UG29QXHJ5rfB2U+heMhUSzjVS7bTaUuA1YkDfFF/G7cIlODZStk2vXJYrcArr1NuKS30BZnQIFI ZLtsgG0DUH+nVLNyiCsqIP9TxvtJMb6p570ilnc= X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--2.838600-4.000000 X-TMASE-Version: SMEX-12.5.0.1300-8.5.1010-24084.005 X-MDID: 1536572033-71EOK6dEl5pQ Subject: [dpdk-dev] [PATCH 22/37] net/sfc/base: add information if TSO workaround is required X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Mark Spender In SF bug 61297 it's been confirmed that the hardware does not always calculate the TCP checksum correctly with TSO sends. The value of the Total Length field (IPv4) or Payload Length field (IPv6) is the critical factor. We're sufficiently confident that if these fields are zero then the checksum will be calculated correctly. The information may be used by the drivers to check if the workaround is required when FATSOv2 is implemented. Signed-off-by: Mark Spender Signed-off-by: Andrew Rybchenko --- drivers/net/sfc/base/efx.h | 1 + drivers/net/sfc/base/hunt_nic.c | 3 +++ drivers/net/sfc/base/medford2_nic.c | 3 +++ drivers/net/sfc/base/medford_nic.c | 3 +++ 4 files changed, 10 insertions(+) diff --git a/drivers/net/sfc/base/efx.h b/drivers/net/sfc/base/efx.h index 3c3227739..2356a9294 100644 --- a/drivers/net/sfc/base/efx.h +++ b/drivers/net/sfc/base/efx.h @@ -1292,6 +1292,7 @@ typedef struct efx_nic_cfg_s { boolean_t enc_bug35388_workaround; boolean_t enc_bug41750_workaround; boolean_t enc_bug61265_workaround; + boolean_t enc_bug61297_workaround; boolean_t enc_rx_batching_enabled; /* Maximum number of descriptors completed in an rx event. */ uint32_t enc_rx_batch_max; diff --git a/drivers/net/sfc/base/hunt_nic.c b/drivers/net/sfc/base/hunt_nic.c index 1bec3c485..70c042f3f 100644 --- a/drivers/net/sfc/base/hunt_nic.c +++ b/drivers/net/sfc/base/hunt_nic.c @@ -190,6 +190,9 @@ hunt_board_cfg( encp->enc_bug61265_workaround = B_FALSE; /* Medford only */ + /* Checksums for TSO sends can be incorrect on Huntington. */ + encp->enc_bug61297_workaround = B_TRUE; + /* Alignment for receive packet DMA buffers */ encp->enc_rx_buf_align_start = 1; encp->enc_rx_buf_align_end = 64; /* RX DMA end padding */ diff --git a/drivers/net/sfc/base/medford2_nic.c b/drivers/net/sfc/base/medford2_nic.c index b36e54bab..3efc35886 100644 --- a/drivers/net/sfc/base/medford2_nic.c +++ b/drivers/net/sfc/base/medford2_nic.c @@ -96,6 +96,9 @@ medford2_board_cfg( else goto fail1; + /* Checksums for TSO sends should always be correct on Medford2. */ + encp->enc_bug61297_workaround = B_FALSE; + /* Get clock frequencies (in MHz). */ if ((rc = efx_mcdi_get_clock(enp, &sysclk, &dpcpu_clk)) != 0) goto fail2; diff --git a/drivers/net/sfc/base/medford_nic.c b/drivers/net/sfc/base/medford_nic.c index 96f3a1204..4f1896343 100644 --- a/drivers/net/sfc/base/medford_nic.c +++ b/drivers/net/sfc/base/medford_nic.c @@ -94,6 +94,9 @@ medford_board_cfg( else goto fail1; + /* Checksums for TSO sends can be incorrect on Medford. */ + encp->enc_bug61297_workaround = B_TRUE; + /* Get clock frequencies (in MHz). */ if ((rc = efx_mcdi_get_clock(enp, &sysclk, &dpcpu_clk)) != 0) goto fail2;