From: Mark Spender <mspender@solarflare.com>
In SF bug 61297 it's been confirmed that the hardware does not always
calculate the TCP checksum correctly with TSO sends.
The value of the Total Length field (IPv4) or Payload Length field
(IPv6) is the critical factor. We're sufficiently confident that if
these fields are zero then the checksum will be calculated correctly.
The information may be used by the drivers to check if the workaround is
required when FATSOv2 is implemented.
Signed-off-by: Mark Spender <mspender@solarflare.com>
Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>
---
drivers/net/sfc/base/efx.h | 1 +
drivers/net/sfc/base/hunt_nic.c | 3 +++
drivers/net/sfc/base/medford2_nic.c | 3 +++
drivers/net/sfc/base/medford_nic.c | 3 +++
4 files changed, 10 insertions(+)
@@ -1292,6 +1292,7 @@ typedef struct efx_nic_cfg_s {
boolean_t enc_bug35388_workaround;
boolean_t enc_bug41750_workaround;
boolean_t enc_bug61265_workaround;
+ boolean_t enc_bug61297_workaround;
boolean_t enc_rx_batching_enabled;
/* Maximum number of descriptors completed in an rx event. */
uint32_t enc_rx_batch_max;
@@ -190,6 +190,9 @@ hunt_board_cfg(
encp->enc_bug61265_workaround = B_FALSE; /* Medford only */
+ /* Checksums for TSO sends can be incorrect on Huntington. */
+ encp->enc_bug61297_workaround = B_TRUE;
+
/* Alignment for receive packet DMA buffers */
encp->enc_rx_buf_align_start = 1;
encp->enc_rx_buf_align_end = 64; /* RX DMA end padding */
@@ -96,6 +96,9 @@ medford2_board_cfg(
else
goto fail1;
+ /* Checksums for TSO sends should always be correct on Medford2. */
+ encp->enc_bug61297_workaround = B_FALSE;
+
/* Get clock frequencies (in MHz). */
if ((rc = efx_mcdi_get_clock(enp, &sysclk, &dpcpu_clk)) != 0)
goto fail2;
@@ -94,6 +94,9 @@ medford_board_cfg(
else
goto fail1;
+ /* Checksums for TSO sends can be incorrect on Medford. */
+ encp->enc_bug61297_workaround = B_TRUE;
+
/* Get clock frequencies (in MHz). */
if ((rc = efx_mcdi_get_clock(enp, &sysclk, &dpcpu_clk)) != 0)
goto fail2;