From patchwork Fri Aug 24 14:54:54 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomasz Duszynski X-Patchwork-Id: 43877 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id E37EF7CDE; Fri, 24 Aug 2018 16:55:15 +0200 (CEST) Received: from mail-lj1-f195.google.com (mail-lj1-f195.google.com [209.85.208.195]) by dpdk.org (Postfix) with ESMTP id 821475F72 for ; Fri, 24 Aug 2018 16:55:10 +0200 (CEST) Received: by mail-lj1-f195.google.com with SMTP id f8-v6so7131353ljk.1 for ; Fri, 24 Aug 2018 07:55:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=RiHTFc5IROF+rR74not8nQ52o6A7SWEJIrPv9/aPEEA=; b=pM5rfPcE/CYK6I1KmZeeHvcsU3fGLDccM8ij4M6JQzCEw4UX7zZ41sD4Dzk6coNKqe 8Tootv+LUI1IHc8KYyknbDvhYyjS6/efLEROhq8PBjIb0RIuxnLSQGqS467ZSVRrkfwl s+YPr7o4KjPklC1woMnS1wEMYZGKUfzAV0hHhJgoKk/y+wgoNYPehVcK5NSeVD8PMzQ2 4vurhKeMNZ0O6mDqz9AestdnmqUlk/Ix0uUFwBv3OW8V4zKYycVkvYHEEAKaRy3X5ve/ uXrnFxnz2F7m5COP68La5ueKC25De7RHWWegasFGyaQVrfTVW/Qhd5F0x2sqfDGH9J0Y viuQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=RiHTFc5IROF+rR74not8nQ52o6A7SWEJIrPv9/aPEEA=; b=HK8t49Bq3wCGwaxyeuzTYFk9agQO3V7WUQ4vN749LMCK+MlCMkE/yoKgU5K3p+e8FY gN0+ZGDwB6yyBcjjqC4KpPM/F67mE+xL2Y9Me0qHJv4PpsieRMZB5UnRnb2uNTB0Mum9 6FwtBtFlYj6Dpl9r6cKq3u9hn2BwuNzEZD2d/35vTEUihz2HPB325HfwKWJfwLqnH3Tg 464OucUvghOEO4kRc9L2O19PZL26j5eEwZ79i0GHGy3t4uvzTQPeZZPU5/PWnNmwaX/1 /wf2mzBHhvTqjXc0uZIh4tLaJtfykRk50sfWk1c2b+vz417AbMa5366smKx6UG+yAlCx x8ZQ== X-Gm-Message-State: APzg51Chieoiu+kxhFONsqH13em/AxwEca/NMjHmBW9bGC/BFncH5Xf2 DM5Fzg9p13vDZCxgj1X9tH/Lob818Ps= X-Google-Smtp-Source: ANB0VdZrAbna5KlW8gPvWCi4BZW3deE6ecQGFiZNn3DJtHvQADL3EWGaxoPXQxzsfMOuDzQDS7kLjQ== X-Received: by 2002:a2e:1609:: with SMTP id w9-v6mr1610034ljd.120.1535122509991; Fri, 24 Aug 2018 07:55:09 -0700 (PDT) Received: from sh.semihalf.local (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id j140-v6sm1373659lfg.16.2018.08.24.07.55.08 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 24 Aug 2018 07:55:08 -0700 (PDT) From: Tomasz Duszynski To: dev@dpdk.org Cc: nsamsono@marvell.com, mw@semihalf.com Date: Fri, 24 Aug 2018 16:54:54 +0200 Message-Id: <1535122494-30249-7-git-send-email-tdu@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1535122494-30249-1-git-send-email-tdu@semihalf.com> References: <1535113006-9393-1-git-send-email-tdu@semihalf.com> <1535122494-30249-1-git-send-email-tdu@semihalf.com> Subject: [dpdk-dev] [PATCH v2 6/6] net/mvpp2: add VLAN packet type support for parser offload X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Natalie Samsonov Add VLAN packet type support for parser offload. Signed-off-by: Natalie Samsonov Reviewed-by: Shlomi Gridish Reviewed-by: Dmitri Epshtein Reviewed-by: Yuval Caduri --- drivers/net/mvpp2/mrvl_ethdev.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/net/mvpp2/mrvl_ethdev.c b/drivers/net/mvpp2/mrvl_ethdev.c index 5cd84c1..5b92d82 100644 --- a/drivers/net/mvpp2/mrvl_ethdev.c +++ b/drivers/net/mvpp2/mrvl_ethdev.c @@ -1353,6 +1353,8 @@ mrvl_dev_supported_ptypes_get(struct rte_eth_dev *dev __rte_unused) { static const uint32_t ptypes[] = { RTE_PTYPE_L2_ETHER, + RTE_PTYPE_L2_ETHER_VLAN, + RTE_PTYPE_L2_ETHER_QINQ, RTE_PTYPE_L3_IPV4, RTE_PTYPE_L3_IPV4_EXT, RTE_PTYPE_L3_IPV4_EXT_UNKNOWN, @@ -1922,13 +1924,27 @@ mrvl_desc_to_packet_type_and_offset(struct pp2_ppio_desc *desc, { enum pp2_inq_l3_type l3_type; enum pp2_inq_l4_type l4_type; + enum pp2_inq_vlan_tag vlan_tag; uint64_t packet_type; pp2_ppio_inq_desc_get_l3_info(desc, &l3_type, l3_offset); pp2_ppio_inq_desc_get_l4_info(desc, &l4_type, l4_offset); + pp2_ppio_inq_desc_get_vlan_tag(desc, &vlan_tag); packet_type = RTE_PTYPE_L2_ETHER; + switch (vlan_tag) { + case PP2_INQ_VLAN_TAG_SINGLE: + packet_type |= RTE_PTYPE_L2_ETHER_VLAN; + break; + case PP2_INQ_VLAN_TAG_DOUBLE: + case PP2_INQ_VLAN_TAG_TRIPLE: + packet_type |= RTE_PTYPE_L2_ETHER_QINQ; + break; + default: + break; + } + switch (l3_type) { case PP2_INQ_L3_TYPE_IPV4_NO_OPTS: packet_type |= RTE_PTYPE_L3_IPV4;